diff mbox series

[v5,08/10] media: dt-bindings: Document i.MX8MQ and i.MX8MM VPU bindings

Message ID 20190612093915.18973-9-p.zabel@pengutronix.de (mailing list archive)
State New, archived
Headers show
Series Rename Rockchip VPU driver to Hantro, add initial i.MX8M support | expand

Commit Message

Philipp Zabel June 12, 2019, 9:39 a.m. UTC 
Add devicetree binding documentation for the Hantro G1/G2 VPU on i.MX8MQ
and for the Hantro G1/G2/H1 VPU on i.MX8MM.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 .../devicetree/bindings/media/imx8m-vpu.txt   | 56 +++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/imx8m-vpu.txt

Comments

Hans Verkuil June 28, 2019, 8:42 a.m. UTC | #1 
Two typos for imx8mm:

On 6/12/19 11:39 AM, Philipp Zabel wrote:
> Add devicetree binding documentation for the Hantro G1/G2 VPU on i.MX8MQ
> and for the Hantro G1/G2/H1 VPU on i.MX8MM.
> 
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
>  .../devicetree/bindings/media/imx8m-vpu.txt   | 56 +++++++++++++++++++
>  1 file changed, 56 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/imx8m-vpu.txt
> 
> diff --git a/Documentation/devicetree/bindings/media/imx8m-vpu.txt b/Documentation/devicetree/bindings/media/imx8m-vpu.txt
> new file mode 100644
> index 000000000000..659bd28dd002
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/imx8m-vpu.txt
> @@ -0,0 +1,56 @@
> +device-tree bindings for Hantro G1/G2/H1 VPU codecs implemented on i.MX8M SoCs
> +
> +Required properties:
> +- compatible: value should be one of the following
> +		"nxp,imx8mq-vpu",
> +		"nxp,imx8mm-vpu";
> +- regs: VPU core and control block register ranges
> +- reg-names: should be
> +		"g1", "g2", "ctrl" on i.MX8MQ,
> +		"g1", "g2", "h1", "ctrl" on i.MX8MM.
> +- interrupts: encoding and decoding interrupt specifiers
> +- interrupt-names: should be
> +		"g1", "g2" on i.MX8MQ,
> +		"g1", "g2", "h1" on i.MX8MM.
> +- clocks: phandle to VPU core clocks and bus clock
> +- clock-names: should be
> +		"g1", "g2", "bus" on i.MX8MQ,
> +		"g1", "g2", "h1", "bus" on i.MX8MM.
> +- power-domains: phandle to power domain node
> +
> +Examples:
> +
> +	vpu: vpu@38300000 {
> +		compatible = "nxp,imx8mq-vpu";
> +		reg = <0x38300000 0x10000>,
> +		      <0x38310000 0x10000>,
> +		      <0x38320000 0x10000>;
> +		reg-names = "g1", "g2", "ctrl";
> +		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "g1", "g2";
> +		clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> +			 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> +			 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> +		clock-names = "g1", "g2", "bus";
> +		power-domains = <&pgc_vpu>;
> +	};
> +
> +	vpu: vpu@38300000 {
> +		compatible = "nxp,imx8mm-vpu";
> +		reg = <0x38300000 0x10000>,
> +		      <0x38310000 0x10000>,
> +		      <0x38320000 0x10000>;

; -> ,

> +		      <0x38330000 0x10000>;
> +		reg-names = "g1", "g2", "h1", "ctrl";
> +		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

; -> ,

> +			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "g1", "g2", "h1";
> +		clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> +			 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> +			 <&clk IMX8MQ_CLK_VPU_H1_ROOT>,
> +			 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> +		clock-names = "g1", "g2", "h1", "bus";
> +		power-domains = <&pgc_vpu>;
> +	};
> 

Regards,

	Hans
Hans Verkuil June 28, 2019, 8:43 a.m. UTC | #2 
On 6/28/19 10:42 AM, Hans Verkuil wrote:
> Two typos for imx8mm:
> 
> On 6/12/19 11:39 AM, Philipp Zabel wrote:
>> Add devicetree binding documentation for the Hantro G1/G2 VPU on i.MX8MQ
>> and for the Hantro G1/G2/H1 VPU on i.MX8MM.
>>
>> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
>> ---
>>  .../devicetree/bindings/media/imx8m-vpu.txt   | 56 +++++++++++++++++++
>>  1 file changed, 56 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/media/imx8m-vpu.txt
>>
>> diff --git a/Documentation/devicetree/bindings/media/imx8m-vpu.txt b/Documentation/devicetree/bindings/media/imx8m-vpu.txt
>> new file mode 100644
>> index 000000000000..659bd28dd002
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/imx8m-vpu.txt
>> @@ -0,0 +1,56 @@
>> +device-tree bindings for Hantro G1/G2/H1 VPU codecs implemented on i.MX8M SoCs
>> +
>> +Required properties:
>> +- compatible: value should be one of the following
>> +		"nxp,imx8mq-vpu",
>> +		"nxp,imx8mm-vpu";
>> +- regs: VPU core and control block register ranges
>> +- reg-names: should be
>> +		"g1", "g2", "ctrl" on i.MX8MQ,
>> +		"g1", "g2", "h1", "ctrl" on i.MX8MM.
>> +- interrupts: encoding and decoding interrupt specifiers
>> +- interrupt-names: should be
>> +		"g1", "g2" on i.MX8MQ,
>> +		"g1", "g2", "h1" on i.MX8MM.
>> +- clocks: phandle to VPU core clocks and bus clock
>> +- clock-names: should be
>> +		"g1", "g2", "bus" on i.MX8MQ,
>> +		"g1", "g2", "h1", "bus" on i.MX8MM.
>> +- power-domains: phandle to power domain node
>> +
>> +Examples:
>> +
>> +	vpu: vpu@38300000 {
>> +		compatible = "nxp,imx8mq-vpu";
>> +		reg = <0x38300000 0x10000>,
>> +		      <0x38310000 0x10000>,
>> +		      <0x38320000 0x10000>;
>> +		reg-names = "g1", "g2", "ctrl";
>> +		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>> +			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
>> +		interrupt-names = "g1", "g2";
>> +		clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
>> +			 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
>> +			 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
>> +		clock-names = "g1", "g2", "bus";
>> +		power-domains = <&pgc_vpu>;
>> +	};
>> +
>> +	vpu: vpu@38300000 {
>> +		compatible = "nxp,imx8mm-vpu";
>> +		reg = <0x38300000 0x10000>,
>> +		      <0x38310000 0x10000>,
>> +		      <0x38320000 0x10000>;
> 
> ; -> ,
> 
>> +		      <0x38330000 0x10000>;
>> +		reg-names = "g1", "g2", "h1", "ctrl";
>> +		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>> +			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> 
> ; -> ,
> 
>> +			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +		interrupt-names = "g1", "g2", "h1";
>> +		clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
>> +			 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
>> +			 <&clk IMX8MQ_CLK_VPU_H1_ROOT>,
>> +			 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;

More typos: IMX8MQ -> IMX8MM for the 4 lines above.

Regards,

	Hans

>> +		clock-names = "g1", "g2", "h1", "bus";
>> +		power-domains = <&pgc_vpu>;
>> +	};
>>
> 
> Regards,
> 
> 	Hans
>
Rob Herring (Arm) July 9, 2019, 2:25 p.m. UTC | #3 
On Wed, Jun 12, 2019 at 11:39:13AM +0200, Philipp Zabel wrote:
> Add devicetree binding documentation for the Hantro G1/G2 VPU on i.MX8MQ
> and for the Hantro G1/G2/H1 VPU on i.MX8MM.
> 
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
>  .../devicetree/bindings/media/imx8m-vpu.txt   | 56 +++++++++++++++++++
>  1 file changed, 56 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/imx8m-vpu.txt
> 
> diff --git a/Documentation/devicetree/bindings/media/imx8m-vpu.txt b/Documentation/devicetree/bindings/media/imx8m-vpu.txt
> new file mode 100644
> index 000000000000..659bd28dd002
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/imx8m-vpu.txt
> @@ -0,0 +1,56 @@
> +device-tree bindings for Hantro G1/G2/H1 VPU codecs implemented on i.MX8M SoCs
> +
> +Required properties:
> +- compatible: value should be one of the following
> +		"nxp,imx8mq-vpu",
> +		"nxp,imx8mm-vpu";
> +- regs: VPU core and control block register ranges
> +- reg-names: should be
> +		"g1", "g2", "ctrl" on i.MX8MQ,
> +		"g1", "g2", "h1", "ctrl" on i.MX8MM.

Would be nicer to put h1 at the end, so the indexes don't change.

> +- interrupts: encoding and decoding interrupt specifiers
> +- interrupt-names: should be
> +		"g1", "g2" on i.MX8MQ,
> +		"g1", "g2", "h1" on i.MX8MM.
> +- clocks: phandle to VPU core clocks and bus clock
> +- clock-names: should be
> +		"g1", "g2", "bus" on i.MX8MQ,
> +		"g1", "g2", "h1", "bus" on i.MX8MM.

Here too.

> +- power-domains: phandle to power domain node
> +
> +Examples:
> +
> +	vpu: vpu@38300000 {

video-codec@...

> +		compatible = "nxp,imx8mq-vpu";
> +		reg = <0x38300000 0x10000>,
> +		      <0x38310000 0x10000>,
> +		      <0x38320000 0x10000>;
> +		reg-names = "g1", "g2", "ctrl";
> +		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "g1", "g2";
> +		clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> +			 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> +			 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> +		clock-names = "g1", "g2", "bus";
> +		power-domains = <&pgc_vpu>;
> +	};
> +
> +	vpu: vpu@38300000 {

Are 2 examples really necessary?

> +		compatible = "nxp,imx8mm-vpu";
> +		reg = <0x38300000 0x10000>,
> +		      <0x38310000 0x10000>,
> +		      <0x38320000 0x10000>;
> +		      <0x38330000 0x10000>;
> +		reg-names = "g1", "g2", "h1", "ctrl";
> +		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "g1", "g2", "h1";
> +		clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> +			 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> +			 <&clk IMX8MQ_CLK_VPU_H1_ROOT>,
> +			 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> +		clock-names = "g1", "g2", "h1", "bus";
> +		power-domains = <&pgc_vpu>;
> +	};
> -- 
> 2.20.1
>
Adam Ford Dec. 20, 2019, 4:52 p.m. UTC | #4 
On Tue, Jul 9, 2019 at 9:26 AM Rob Herring <robh@kernel.org> wrote:
>
> On Wed, Jun 12, 2019 at 11:39:13AM +0200, Philipp Zabel wrote:
> > Add devicetree binding documentation for the Hantro G1/G2 VPU on i.MX8MQ
> > and for the Hantro G1/G2/H1 VPU on i.MX8MM.
> >
> > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

Are there any updates to this?  It would be nice to have the VPU
working in the mainline, but it seems to have stalled.

adam
> > ---
> >  .../devicetree/bindings/media/imx8m-vpu.txt   | 56 +++++++++++++++++++
> >  1 file changed, 56 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/media/imx8m-vpu.txt
> >
> > diff --git a/Documentation/devicetree/bindings/media/imx8m-vpu.txt b/Documentation/devicetree/bindings/media/imx8m-vpu.txt
> > new file mode 100644
> > index 000000000000..659bd28dd002
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/imx8m-vpu.txt
> > @@ -0,0 +1,56 @@
> > +device-tree bindings for Hantro G1/G2/H1 VPU codecs implemented on i.MX8M SoCs
> > +
> > +Required properties:
> > +- compatible: value should be one of the following
> > +             "nxp,imx8mq-vpu",
> > +             "nxp,imx8mm-vpu";
> > +- regs: VPU core and control block register ranges
> > +- reg-names: should be
> > +             "g1", "g2", "ctrl" on i.MX8MQ,
> > +             "g1", "g2", "h1", "ctrl" on i.MX8MM.
>
> Would be nicer to put h1 at the end, so the indexes don't change.
>
> > +- interrupts: encoding and decoding interrupt specifiers
> > +- interrupt-names: should be
> > +             "g1", "g2" on i.MX8MQ,
> > +             "g1", "g2", "h1" on i.MX8MM.
> > +- clocks: phandle to VPU core clocks and bus clock
> > +- clock-names: should be
> > +             "g1", "g2", "bus" on i.MX8MQ,
> > +             "g1", "g2", "h1", "bus" on i.MX8MM.
>
> Here too.
>
> > +- power-domains: phandle to power domain node
> > +
> > +Examples:
> > +
> > +     vpu: vpu@38300000 {
>
> video-codec@...
>
> > +             compatible = "nxp,imx8mq-vpu";
> > +             reg = <0x38300000 0x10000>,
> > +                   <0x38310000 0x10000>,
> > +                   <0x38320000 0x10000>;
> > +             reg-names = "g1", "g2", "ctrl";
> > +             interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > +             interrupt-names = "g1", "g2";
> > +             clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > +                      <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > +                      <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > +             clock-names = "g1", "g2", "bus";
> > +             power-domains = <&pgc_vpu>;
> > +     };
> > +
> > +     vpu: vpu@38300000 {
>
> Are 2 examples really necessary?
>
> > +             compatible = "nxp,imx8mm-vpu";
> > +             reg = <0x38300000 0x10000>,
> > +                   <0x38310000 0x10000>,
> > +                   <0x38320000 0x10000>;
> > +                   <0x38330000 0x10000>;
> > +             reg-names = "g1", "g2", "h1", "ctrl";
> > +             interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > +                          <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > +             interrupt-names = "g1", "g2", "h1";
> > +             clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > +                      <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > +                      <&clk IMX8MQ_CLK_VPU_H1_ROOT>,
> > +                      <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > +             clock-names = "g1", "g2", "h1", "bus";
> > +             power-domains = <&pgc_vpu>;
> > +     };
> > --
> > 2.20.1
> >
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/media/imx8m-vpu.txt b/Documentation/devicetree/bindings/media/imx8m-vpu.txt
new file mode 100644
index 000000000000..659bd28dd002
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/imx8m-vpu.txt
@@ -0,0 +1,56 @@ 
+device-tree bindings for Hantro G1/G2/H1 VPU codecs implemented on i.MX8M SoCs
+
+Required properties:
+- compatible: value should be one of the following
+		"nxp,imx8mq-vpu",
+		"nxp,imx8mm-vpu";
+- regs: VPU core and control block register ranges
+- reg-names: should be
+		"g1", "g2", "ctrl" on i.MX8MQ,
+		"g1", "g2", "h1", "ctrl" on i.MX8MM.
+- interrupts: encoding and decoding interrupt specifiers
+- interrupt-names: should be
+		"g1", "g2" on i.MX8MQ,
+		"g1", "g2", "h1" on i.MX8MM.
+- clocks: phandle to VPU core clocks and bus clock
+- clock-names: should be
+		"g1", "g2", "bus" on i.MX8MQ,
+		"g1", "g2", "h1", "bus" on i.MX8MM.
+- power-domains: phandle to power domain node
+
+Examples:
+
+	vpu: vpu@38300000 {
+		compatible = "nxp,imx8mq-vpu";
+		reg = <0x38300000 0x10000>,
+		      <0x38310000 0x10000>,
+		      <0x38320000 0x10000>;
+		reg-names = "g1", "g2", "ctrl";
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "g1", "g2";
+		clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+			 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+			 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+		clock-names = "g1", "g2", "bus";
+		power-domains = <&pgc_vpu>;
+	};
+
+	vpu: vpu@38300000 {
+		compatible = "nxp,imx8mm-vpu";
+		reg = <0x38300000 0x10000>,
+		      <0x38310000 0x10000>,
+		      <0x38320000 0x10000>;
+		      <0x38330000 0x10000>;
+		reg-names = "g1", "g2", "h1", "ctrl";
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "g1", "g2", "h1";
+		clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+			 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+			 <&clk IMX8MQ_CLK_VPU_H1_ROOT>,
+			 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+		clock-names = "g1", "g2", "h1", "bus";
+		power-domains = <&pgc_vpu>;
+	};