From patchwork Mon Nov 4 20:48:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11226467 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BED31112B for ; Mon, 4 Nov 2019 20:49:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9DA89214E0 for ; Mon, 4 Nov 2019 20:49:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="OoyV+y7p" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729810AbfKDUtX (ORCPT ); Mon, 4 Nov 2019 15:49:23 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58250 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729792AbfKDUtX (ORCPT ); Mon, 4 Nov 2019 15:49:23 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xA4KnIxp129114; Mon, 4 Nov 2019 14:49:18 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1572900558; bh=FND3XnjPqEdXZhVPPo6uZwFZk9lpeYV53xeWgNl+dek=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OoyV+y7pfns5k5HZmsyZfss1WsalU7DZOl3u6knXu0VMNnGNyfcSPebzTS9Jp0/a1 F5dj+Eu++2XrIimKhsE2HtvsPk4ezw9UebvermRPrs1NPWg7Oa5tJ8QPxSeCj8qhvc Ptdh8cyoa7qDrWlOR/i7AHJTbAU/1pa8p8agOfjQ= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xA4KnIdT005255; Mon, 4 Nov 2019 14:49:18 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 4 Nov 2019 14:49:03 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 4 Nov 2019 14:49:17 -0600 Received: from ula0869644.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xA4Kmv03038360; Mon, 4 Nov 2019 14:49:17 -0600 From: Benoit Parrot To: Tony Lindgren , Tero Kristo CC: , , , , Rob Herring , , , Benoit Parrot Subject: [Patch v2 07/10] arm: dtsi: dra76x: Add CAL dtsi node Date: Mon, 4 Nov 2019 14:48:50 -0600 Message-ID: <20191104204853.4355-8-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104204853.4355-1-bparrot@ti.com> References: <20191104204853.4355-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add the required dtsi node to support the Camera Adaptation Layer (CAL) for the DRA76 family of devices. Signed-off-by: Benoit Parrot --- arch/arm/boot/dts/dra76x.dtsi | 43 +++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index cdcba3f561c4..2f58c709c081 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -41,6 +41,49 @@ }; +&l4_per3 { + target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x1b0000 0x4>, + <0x1b0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b0000 0x10000>; + + cal: cal@0 { + compatible = "ti,dra76-cal"; + reg = <0x0000 0x400>, + <0x0800 0x40>, + <0x0900 0x40>; + reg-names = "cal_top", + "cal_rx_core0", + "cal_rx_core1"; + interrupts = ; + ti,camerrx-control = <&scm_conf 0x6dc>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + }; + csi2_1: port@1 { + reg = <1>; + }; + }; + }; + }; +}; + /* MCAN interrupts are hard-wired to irqs 67, 68 */ &crossbar_mpu { ti,irqs-skip = <10 67 68 133 139 140>;