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[73.25.156.94]) by smtp.gmail.com with ESMTPSA id a24sm68148pgv.76.2021.05.19.11.35.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:35:13 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= , linux-kernel@vger.kernel.org (open list), linux-media@vger.kernel.org (open list:DMA BUFFER SHARING FRAMEWORK), linaro-mm-sig@lists.linaro.org (moderated list:DMA BUFFER SHARING FRAMEWORK) Subject: [RFC 3/3] drm/msm: Wire up gpu boost Date: Wed, 19 May 2021 11:38:54 -0700 Message-Id: <20210519183855.1523927-4-robdclark@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210519183855.1523927-1-robdclark@gmail.com> References: <20210519183855.1523927-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Rob Clark Note, at this point I haven't given a lot of consideration into how much we should boost, and for how long. And perhaps we should only boost at less than 50% utilization? At this point, this is only an example of dma_fence_boost() implementation. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_fence.c | 10 ++++++++++ drivers/gpu/drm/msm/msm_gpu.c | 13 +++++++++++++ drivers/gpu/drm/msm/msm_gpu.h | 2 ++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fence.c index cd59a5918038..e58895603726 100644 --- a/drivers/gpu/drm/msm/msm_fence.c +++ b/drivers/gpu/drm/msm/msm_fence.c @@ -8,6 +8,7 @@ #include "msm_drv.h" #include "msm_fence.h" +#include "msm_gpu.h" struct msm_fence_context * @@ -114,10 +115,19 @@ static bool msm_fence_signaled(struct dma_fence *fence) return fence_completed(f->fctx, f->base.seqno); } +static void msm_fence_boost(struct dma_fence *fence) +{ + struct msm_fence *f = to_msm_fence(fence); + struct msm_drm_private *priv = f->fctx->dev->dev_private; + + msm_gpu_boost(priv->gpu); +} + static const struct dma_fence_ops msm_fence_ops = { .get_driver_name = msm_fence_get_driver_name, .get_timeline_name = msm_fence_get_timeline_name, .signaled = msm_fence_signaled, + .boost = msm_fence_boost, }; struct dma_fence * diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 9dd1c58430ab..c90b79116500 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -62,6 +62,10 @@ static int msm_devfreq_get_dev_status(struct device *dev, status->total_time = ktime_us_delta(time, gpu->devfreq.time); gpu->devfreq.time = time; + if (atomic_dec_if_positive(&gpu->devfreq.boost) >= 0) { + status->busy_time = status->total_time; + } + return 0; } @@ -84,6 +88,15 @@ static struct devfreq_dev_profile msm_devfreq_profile = { .get_cur_freq = msm_devfreq_get_cur_freq, }; +void msm_gpu_boost(struct msm_gpu *gpu) +{ + if (!gpu->funcs->gpu_busy) + return; + + /* Add three devfreq polling intervals worth of boost: */ + atomic_add(3, &gpu->devfreq.boost); +} + static void msm_devfreq_init(struct msm_gpu *gpu) { /* We need target support to do devfreq */ diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 18baf935e143..7a082a12d98f 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -150,6 +150,7 @@ struct msm_gpu { struct devfreq *devfreq; u64 busy_cycles; ktime_t time; + atomic_t boost; } devfreq; uint32_t suspend_count; @@ -295,6 +296,7 @@ static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) int msm_gpu_pm_suspend(struct msm_gpu *gpu); int msm_gpu_pm_resume(struct msm_gpu *gpu); void msm_gpu_resume_devfreq(struct msm_gpu *gpu); +void msm_gpu_boost(struct msm_gpu *gpu); int msm_gpu_hw_init(struct msm_gpu *gpu);