| Message ID | 20210915120240.21572-4-p.yadav@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | CSI2RX support on J721E | expand |
Hi Pratyush, Thank you for the patch. On Wed, Sep 15, 2021 at 05:32:32PM +0530, Pratyush Yadav wrote: > This resets the stream state machines and FIFOs, giving them a clean > slate. On J721E if the streams are not reset before starting the > capture, the captured frame gets wrapped around vertically on every run > after the first. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > --- > > (no changes since v1) > > drivers/media/platform/cadence/cdns-csi2rx.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c > index c06e039a1aa8..e05d76394cd6 100644 > --- a/drivers/media/platform/cadence/cdns-csi2rx.c > +++ b/drivers/media/platform/cadence/cdns-csi2rx.c > @@ -39,6 +39,7 @@ > #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) > > #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) > +#define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) > #define CSI2RX_STREAM_CTRL_START BIT(0) > > #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) > @@ -135,12 +136,22 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) > > static void csi2rx_reset(struct csi2rx_priv *csi2rx) > { > + int i; i is always positive, it can be an unsigned int. With this, Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > + > writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT, > csi2rx->base + CSI2RX_SOFT_RESET_REG); > > udelay(10); > > writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); > + > + /* Reset individual streams. */ > + for (i = 0; i < csi2rx->max_streams; i++) { > + writel(CSI2RX_STREAM_CTRL_SOFT_RST, > + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); > + usleep_range(10, 20); > + writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); > + } > } > > static int csi2rx_configure_external_dphy(struct csi2rx_priv *csi2rx)
diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index c06e039a1aa8..e05d76394cd6 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -39,6 +39,7 @@ #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) +#define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) #define CSI2RX_STREAM_CTRL_START BIT(0) #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) @@ -135,12 +136,22 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) static void csi2rx_reset(struct csi2rx_priv *csi2rx) { + int i; + writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT, csi2rx->base + CSI2RX_SOFT_RESET_REG); udelay(10); writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); + + /* Reset individual streams. */ + for (i = 0; i < csi2rx->max_streams; i++) { + writel(CSI2RX_STREAM_CTRL_SOFT_RST, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + usleep_range(10, 20); + writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + } } static int csi2rx_configure_external_dphy(struct csi2rx_priv *csi2rx)
This resets the stream state machines and FIFOs, giving them a clean slate. On J721E if the streams are not reset before starting the capture, the captured frame gets wrapped around vertically on every run after the first. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- (no changes since v1) drivers/media/platform/cadence/cdns-csi2rx.c | 11 +++++++++++ 1 file changed, 11 insertions(+)