From patchwork Wed Dec 8 22:50:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12665471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46E79C433FE for ; Wed, 8 Dec 2021 22:51:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240822AbhLHWyV (ORCPT ); Wed, 8 Dec 2021 17:54:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240776AbhLHWyS (ORCPT ); Wed, 8 Dec 2021 17:54:18 -0500 Received: from mail-io1-xd36.google.com (mail-io1-xd36.google.com [IPv6:2607:f8b0:4864:20::d36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDBE1C0617A2; Wed, 8 Dec 2021 14:50:45 -0800 (PST) Received: by mail-io1-xd36.google.com with SMTP id x6so4512718iol.13; Wed, 08 Dec 2021 14:50:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4KtwNb8j6a2zsGgzuGMwDgSdQr1FlL5K/biJ1D+wEHo=; b=Kll51ijEMqpTNJzyMDpXHqBYLexy4o/qzEJUaCHlgmnEOwjp4m/SuuBqXZZC1yCP2j Kp93ci8hJM5A06J//h73tGZZu02EFWsyu7pbDae7pb/FmvOhMn7nJ0P85+lRyGTZ/S0i 7W6cNivyvb/tOGdcoaGDHTxHsjWDLATDH1+NxmgMku/3Ax7kOhvRjgf/rKY3U0gC+a7c 4RAvz3ZRJ21rqN2PYGfIv7OkD9s8LnNT9Q49FMSBjr8Wao+LhJyVLhVc1jogaQIwF7V1 EIdHfsSOL7LYTxLHSjgZlor+W45Ml3FyJF8g//w5RbcNygvejx+9lokMP1qQ8kNICn1+ iWhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4KtwNb8j6a2zsGgzuGMwDgSdQr1FlL5K/biJ1D+wEHo=; b=u1PMn7trGe4w28pnWLxg2T1jz/4KOM9qubPg6i3b8QjKdtQieRhucElkXK5z08rknT c7etJ1XTgDB41qof5KtbLKzkPcMFD4al8GXd1GT8wp8InaJaWgjZyrgEGUu5+wiT12zj bAheCyY+kFwk7WHOVhN0cOz00tAKDA6kFbZkuDorTPMHL1Pgxgfg1RUvNzNIHxFWgzH1 Cw5yG7ve6npRiw0BESTAaJ61bZhqhLb1p9dLzC68y3V/FgHRGnATvQnJ0Qic5agwtveD VfY5AzZmIuA/dWuQjF47mlTv68beHICq7gKlgTdrZf1nPfpxP/t2sggYbUfZpbhBdP+t 9QSA== X-Gm-Message-State: AOAM533yEJ5HK98o3elHcuxuGylCnetM+kcBZvAmrBYiYtno6osM24Sg dLhGrr0GKs76Gq8mfn7Y1K+QL0Dc8/g8dA== X-Google-Smtp-Source: ABdhPJx6QhI6xxZLbjEV833xRsuNTkhfDi2RyYZSZYB1Lm113SMDd7tqWpPILf/ioHdOeXEWTuKoBw== X-Received: by 2002:a05:6602:26d0:: with SMTP id g16mr9547627ioo.70.1639003844819; Wed, 08 Dec 2021 14:50:44 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:269a:1aa2:f1d9:8dbb]) by smtp.gmail.com with ESMTPSA id t6sm2378751ioi.51.2021.12.08.14.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 14:50:44 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Lucas Stach , Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 03/10] soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl Date: Wed, 8 Dec 2021 16:50:22 -0600 Message-Id: <20211208225030.2018923-4-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Lucas Stach This adds the necessary bits to drive the VPU blk-ctrl on the i.MX8MQ, to avoid putting more of this functionality into the decoder driver. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford --- drivers/soc/imx/imx8m-blk-ctrl.c | 68 +++++++++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index 519b3651d1d9..a7c12e8fa89b 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -14,6 +14,7 @@ #include #include +#include #define BLK_SFT_RSTN 0x0 #define BLK_CLK_EN 0x4 @@ -498,6 +499,68 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), }; +static int imx8mq_vpu_power_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, + power_nb); + + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) + return NOTIFY_OK; + + /* + * The ADB in the VPUMIX domain has no separate reset and clock + * enable bits, but is ungated and reset together with the VPUs. The + * reset and clock enable inputs to the ADB is a logical OR of the + * VPU bits. In order to set the G2 fuse bits, the G2 clock must + * also be enabled. + */ + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1)); + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1)); + + if (action == GENPD_NOTIFY_ON) { + /* + * On power up we have no software backchannel to the GPC to + * wait for the ADB handshake to happen, so we just delay for a + * bit. On power down the GPC driver waits for the handshake. + */ + udelay(5); + + /* set "fuse" bits to enable the VPUs */ + regmap_set_bits(bc->regmap, 0x8, 0xffffffff); + regmap_set_bits(bc->regmap, 0xc, 0xffffffff); + regmap_set_bits(bc->regmap, 0x10, 0xffffffff); + } + + return NOTIFY_OK; +} + +static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = { + [IMX8MQ_VPUBLK_PD_G1] = { + .name = "vpublk-g1", + .clk_names = (const char *[]){ "g1", }, + .num_clks = 1, + .gpc_name = "g1", + .rst_mask = BIT(1), + .clk_mask = BIT(1), + }, + [IMX8MQ_VPUBLK_PD_G2] = { + .name = "vpublk-g2", + .clk_names = (const char *[]){ "g2", }, + .num_clks = 1, + .gpc_name = "g2", + .rst_mask = BIT(0), + .clk_mask = BIT(0), + }, +}; + +static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = { + .max_reg = 0x14, + .power_notifier_fn = imx8mq_vpu_power_notifier, + .domains = imx8mq_vpu_blk_ctl_domain_data, + .num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data), +}; + static const struct of_device_id imx8m_blk_ctrl_of_match[] = { { .compatible = "fsl,imx8mm-vpu-blk-ctrl", @@ -505,7 +568,10 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { }, { .compatible = "fsl,imx8mm-disp-blk-ctrl", .data = &imx8mm_disp_blk_ctl_dev_data - } ,{ + }, { + .compatible = "fsl,imx8mq-vpu-blk-ctrl", + .data = &imx8mq_vpu_blk_ctl_dev_data + }, { /* Sentinel */ } };