From patchwork Thu Dec 16 11:12:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12680671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 934C6C433EF for ; Thu, 16 Dec 2021 11:13:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236577AbhLPLNm (ORCPT ); Thu, 16 Dec 2021 06:13:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236547AbhLPLNa (ORCPT ); Thu, 16 Dec 2021 06:13:30 -0500 Received: from mail-io1-xd2c.google.com (mail-io1-xd2c.google.com [IPv6:2607:f8b0:4864:20::d2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 114B4C061401; Thu, 16 Dec 2021 03:13:30 -0800 (PST) Received: by mail-io1-xd2c.google.com with SMTP id x6so34407357iol.13; Thu, 16 Dec 2021 03:13:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rzx5jUD4NI/pFUe7ZWnx346ZCIBslKEARnIfPCiUHoo=; b=DnuiV6eiFqI00zTgvM7m1LhO6d/zeQM2+V2LNGcA9GATvj1AYF3A5x/zl1yzezm57t ZCkYJ03zDGLelHhDZNzVAnhZvyRb9Lyf4AmMDp8CmNmNXCHN4il2WDj7QV5J+IOrL1Lq hFaM2u0dym9Up7+3KFflN/a2sb+fy05GcAQGfnLTOvHnNN5iK1uOR9TWG39ajuFNoaIc q4qx1WEKm1FQcNk0VtgPNnQNGge8oUZ5rhNRVE3dUl2tGQc0VLLTTLlF3r4SOlbkFWl6 XjszjdQjWmefW5I7CR3yblxZYNDznHgJYBvU7C1/TVq0PP875zRp6AszUcgWcVdc5lPV AvIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Rzx5jUD4NI/pFUe7ZWnx346ZCIBslKEARnIfPCiUHoo=; b=eiY4RPSF5Z3XCbMRe3JJSZ8UQG5E6SqMcv3XVSSbgt06WSX5vTjpRGO0GN++q1O+tB RIrsNN4HA602jhbzklxcIeq8qeDfcMe16TiB7laLtIA21fz03AyGMd9IQrD6vGT3HPRf PrXiiCuH0KHY9nKNvYnNc28MI5NBbs+z9lfqabQ6lbjS59b5vwLrEwFU4l1BidIGEzy1 o7lDA7W1rQZ6SszSZoY89OFWKUOfWsszmunXauroC3lSAkMGJWeZfXPZYrz+RM/ptAnG 7JOzFkc6RBgbFNUjHbQkxFS0vfXh3W28w7zc4bi/tMk8PoLIEU3O6wd3OkNS+Gn8G1+V /CDQ== X-Gm-Message-State: AOAM532Vz0iuCHHev8IGCQBlkAUHMJlVv4iNjjo3T1pjKMz8UL6cpvoy E2kc2Sv4S0oNPzfJzUbVILEAHVs+FImlNhvL X-Google-Smtp-Source: ABdhPJxnTsd/C+zIC5V2sOoMCQpF5gaWY0Z8fXHYbMfArLEgXOTaqamjaTuo5pq7NJtHFdhYgHqAjA== X-Received: by 2002:a02:c6c5:: with SMTP id r5mr9114049jan.110.1639653208910; Thu, 16 Dec 2021 03:13:28 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:fe22:1652:55f7:5197]) by smtp.gmail.com with ESMTPSA id h1sm3090946iow.31.2021.12.16.03.13.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 03:13:28 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: abel.vesa@nxp.com, aford@beaconembedded.com, benjamin.gaignard@collabora.com, hverkuil-cisco@xs4all.nl, Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH V2 06/10] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl Date: Thu, 16 Dec 2021 05:12:51 -0600 Message-Id: <20211216111256.2362683-7-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211216111256.2362683-1-aford173@gmail.com> References: <20211216111256.2362683-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org With the Hantro G1 and G2 now setup to run independently, update the device tree to allow both to operate. This requires the vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs certain clock enabled to handle the gating of the G1 and G2 fuses, the clock-parents and clock-rates for the various VPU's to be moved into the pgc_vpu because they cannot get re-parented once enabled, and the pgc_vpu is the highest in the chain. Signed-off-by: Adam Ford diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 972766b67a15..5029c121d48b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -711,7 +711,21 @@ pgc_gpu: power-domain@5 { pgc_vpu: power-domain@6 { #power-domain-cells = <0>; reg = ; - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, + <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, + <&clk IMX8MQ_CLK_VPU_G2>, + <&clk IMX8MQ_CLK_VPU_BUS>, + <&clk IMX8MQ_VPU_PLL_BYPASS>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_VPU_PLL>; + assigned-clock-rates = <600000000>, + <600000000>, + <800000000>, + <0>; }; pgc_disp: power-domain@7 { @@ -1432,30 +1446,31 @@ usb3_phy1: usb-phy@382f0040 { status = "disabled"; }; - vpu: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu"; - reg = <0x38300000 0x10000>, - <0x38310000 0x10000>, - <0x38320000 0x10000>; - reg-names = "g1", "g2", "ctrl"; - interrupts = , - ; - interrupt-names = "g1", "g2"; + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mq-vpu-g1"; + reg = <0x38300000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; + }; + + vpu_blk_ctrl: blk-ctrl@38320000 { + compatible = "fsl,imx8mq-vpu-blk-ctrl"; + reg = <0x38320000 0x100>; + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; + power-domain-names = "bus", "g1", "g2"; clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; - clock-names = "g1", "g2", "bus"; - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, - <&clk IMX8MQ_CLK_VPU_G2>, - <&clk IMX8MQ_CLK_VPU_BUS>, - <&clk IMX8MQ_VPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_VPU_PLL>; - assigned-clock-rates = <600000000>, <600000000>, - <800000000>, <0>; - power-domains = <&pgc_vpu>; + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g1", "g2"; + #power-domain-cells = <1>; }; pcie0: pcie@33800000 {