Message ID | 20220414053528.31460-2-yuji2.ishikawa@toshiba.co.jp (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Visconti: Add Toshiba Visconti Video Input Interface driver | expand |
On 14/04/2022 07:35, Yuji Ishikawa wrote: > Adds the Device Tree binding documentation that allows to describe > the Video Input Interface found in Toshiba Visconti SoCs. > > Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp> > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > --- > .../bindings/media/toshiba,visconti-viif.yaml | 103 ++++++++++++++++++ > 1 file changed, 103 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml > > diff --git a/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml b/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml > new file mode 100644 You need to CC this series to devicetree@vger.kernel.org so that the device tree reviewers can take a look at this. Regards, Hans > index 000000000..848ea5019 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml > @@ -0,0 +1,103 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/toshiba,visconti-viif.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Toshiba Visconti5 SoC Video Input Interface Device Tree Bindings > + > +maintainers: > + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > + > +description: | > + Toshiba Visconti5 SoC Video Input Interface (VIIF) receives MIPI CSI2 video stream, > + processes the stream with embedded image signal processor (L1ISP, L2ISP), then stores pictures to main memory. > + > +properties: > + compatible: > + const: toshiba,visconti-viif > + > + reg: > + items: > + - description: registers for capture control > + - description: registers for CSI2 receiver control > + > + interrupts: > + items: > + - description: Sync Interrupt > + - description: Status (Error) Interrupt > + - description: CSI2 Receiver Interrupt > + - description: L1ISP Interrupt > + > + index: > + enum: [0, 1] > + > + port: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: Input port node, single endpoint describing the CSI-2 transmitter. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + description: VIIF supports 2 or 4 data lines > + items: > + minItems: 1 > + maxItems: 4 > + items: > + - const: 1 > + - const: 2 > + - const: 3 > + - const: 4 > + clock-lanes: > + description: VIIF supports 1 clock line > + const: 0 > + > +required: > + - compatible > + - reg > + - interrupts > + - port > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + viif0: viif@1c000000 { > + compatible = "toshiba,visconti-viif"; > + reg = <0 0x1c000000 0 0x6000>, > + <0 0x1c008000 0 0x400>; > + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; > + index = <0>; > + status = "disabled"; > + > + port { > + #address-cells = <1>; > + #size-cells = <0>; > + > + csi_in0: endpoint { > + remote-endpoint = <&imx219_out0>; > + bus-type = <4>; > + data-lanes = <1 2>; > + clock-lanes = <0>; > + clock-noncontinuous; > + link-frequencies = /bits/ 64 <456000000>; > + }; > + }; > + }; > + }; > +
Hi, Hans Thank you for your comments. I'll add the specified address for further posts. Regards, Yuji > -----Original Message----- > From: Hans Verkuil <hverkuil@xs4all.nl> > Sent: Wednesday, April 20, 2022 4:56 PM > To: ishikawa yuji(石川 悠司 ○RDC□AITC○EA開) > <yuji2.ishikawa@toshiba.co.jp>; Mauro Carvalho Chehab > <mchehab@kernel.org>; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT) > <nobuhiro1.iwamatsu@toshiba.co.jp> > Cc: linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux-kernel@vger.kernel.org > Subject: Re: [PATCH v2 1/5] dt-bindings: media: platform: visconti: Add > Toshiba Visconti Video Input Interface bindings > > On 14/04/2022 07:35, Yuji Ishikawa wrote: > > Adds the Device Tree binding documentation that allows to describe the > > Video Input Interface found in Toshiba Visconti SoCs. > > > > Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp> > > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > > --- > > .../bindings/media/toshiba,visconti-viif.yaml | 103 > > ++++++++++++++++++ > > 1 file changed, 103 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml > > b/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml > > new file mode 100644 > > You need to CC this series to devicetree@vger.kernel.org so that the device tree > reviewers can take a look at this. > > Regards, > > Hans > > > index 000000000..848ea5019 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/toshiba,visconti-viif.ya > > +++ ml > > @@ -0,0 +1,103 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/toshiba,visconti-viif.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Toshiba Visconti5 SoC Video Input Interface Device Tree > > +Bindings > > + > > +maintainers: > > + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > > + > > +description: | > > + Toshiba Visconti5 SoC Video Input Interface (VIIF) receives MIPI > > +CSI2 video stream, > > + processes the stream with embedded image signal processor (L1ISP, > L2ISP), then stores pictures to main memory. > > + > > +properties: > > + compatible: > > + const: toshiba,visconti-viif > > + > > + reg: > > + items: > > + - description: registers for capture control > > + - description: registers for CSI2 receiver control > > + > > + interrupts: > > + items: > > + - description: Sync Interrupt > > + - description: Status (Error) Interrupt > > + - description: CSI2 Receiver Interrupt > > + - description: L1ISP Interrupt > > + > > + index: > > + enum: [0, 1] > > + > > + port: > > + $ref: /schemas/graph.yaml#/$defs/port-base > > + unevaluatedProperties: false > > + description: Input port node, single endpoint describing the CSI-2 > transmitter. > > + > > + properties: > > + endpoint: > > + $ref: video-interfaces.yaml# > > + unevaluatedProperties: false > > + > > + properties: > > + data-lanes: > > + description: VIIF supports 2 or 4 data lines > > + items: > > + minItems: 1 > > + maxItems: 4 > > + items: > > + - const: 1 > > + - const: 2 > > + - const: 3 > > + - const: 4 > > + clock-lanes: > > + description: VIIF supports 1 clock line > > + const: 0 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - port > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + viif0: viif@1c000000 { > > + compatible = "toshiba,visconti-viif"; > > + reg = <0 0x1c000000 0 0x6000>, > > + <0 0x1c008000 0 0x400>; > > + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; > > + index = <0>; > > + status = "disabled"; > > + > > + port { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + csi_in0: endpoint { > > + remote-endpoint = <&imx219_out0>; > > + bus-type = <4>; > > + data-lanes = <1 2>; > > + clock-lanes = <0>; > > + clock-noncontinuous; > > + link-frequencies = /bits/ 64 <456000000>; > > + }; > > + }; > > + }; > > + }; > > +
diff --git a/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml b/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml new file mode 100644 index 000000000..848ea5019 --- /dev/null +++ b/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/toshiba,visconti-viif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti5 SoC Video Input Interface Device Tree Bindings + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + +description: | + Toshiba Visconti5 SoC Video Input Interface (VIIF) receives MIPI CSI2 video stream, + processes the stream with embedded image signal processor (L1ISP, L2ISP), then stores pictures to main memory. + +properties: + compatible: + const: toshiba,visconti-viif + + reg: + items: + - description: registers for capture control + - description: registers for CSI2 receiver control + + interrupts: + items: + - description: Sync Interrupt + - description: Status (Error) Interrupt + - description: CSI2 Receiver Interrupt + - description: L1ISP Interrupt + + index: + enum: [0, 1] + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Input port node, single endpoint describing the CSI-2 transmitter. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: VIIF supports 2 or 4 data lines + items: + minItems: 1 + maxItems: 4 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + clock-lanes: + description: VIIF supports 1 clock line + const: 0 + +required: + - compatible + - reg + - interrupts + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + viif0: viif@1c000000 { + compatible = "toshiba,visconti-viif"; + reg = <0 0x1c000000 0 0x6000>, + <0 0x1c008000 0 0x400>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + index = <0>; + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + csi_in0: endpoint { + remote-endpoint = <&imx219_out0>; + bus-type = <4>; + data-lanes = <1 2>; + clock-lanes = <0>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; + }; +