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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zTPgCjdUxnFUEZ9OBcOrAnhFwYVqetb9KN8gCUo+r4oZkf6sN/so4yLP4OyqWyMchmBsFxPr+CsZ8muk2Nylk5FA24X0ryeog3gJ2z98ZkjHMttuXhxHEmOtQCjST+nfyU/A1ovM74By9Ml5f6yvQtGIXZVO/PpzOJl53DUqau3lYZhbb4LnWbhzc5Yygx1K8HmNBIk5oj3zihlW4xK5GlwR6OJkE6GhDOU+PoT58FnuYC0LBA7FcN14mWqPcUeiBgzNLUf3y5nJ4NjRGorziGvFT2d1B2KnQzHsguTUdrqp8yDRBiK/4wvVfCekJbyhDsW4zpiTBnywNl6B7VVce2Dn7jYraNTGYWj59nqSczwHv/y5E934aND5xNfAt42jsmR8lIQ9RNfly055Zrw6vtYUoHWMFlzon8PqNl5qSmlizgPWgUTJ7uskni5aycx32+BN6BvqhAYP0K3cITad5+spX6DVXQR55/0ryipd/buGF3K5YTpTZp2lLU9OTYvlJTHhXjmRkMgWrRlcTs3lpAZOGT+TAGbIN0/K1y/W2CFNdRPpG5YuMYmcp0WOApuisuTynGWov26ifzYHz77YlEFgKnXrx1a9CAavbfblhjWnHdu4tw1fbEkY5wHTI8WZk4PIBPjXfSAAAjROI5HEeADoocw2qnexov82Ql8atQPfwLK795OwEV4jKVTiMALZE8JuT0zkYsxFf5lsiPRIPiQ68PY/hc7Ea/8qBi6F53fLwC5iAP0Igb1F01bIMYVsZqUL4iyaNq1gwIF0BCas38inzFDDgIqdc/zOXIH/lINokf0FcqmA3UeZ91qEA2ENF49a1OupJdCXMwbVv2hJwsbaRKjBQ2aVzp5U1fO6atCnWoCXct0UYH/TdI6WSjTxyn8HzH9NJiq+pvv8xTorBlGga9C+kUcrdh8gHMH8yJMCmoWKPSpyprCNkSmGjwfbK/MpexYWtLF1YzR3fk/fE3chEE4rpi9aEaXvmoeIBrAJ3sfBcvQrB3W4NTSBQSxExMt+NX2hTy+E4vYvdDUGqLVK6vOtIPzL2IRc0Bii0Ae14Opn62xX9T0bdfZjLgn1f6uqgZ5a4VKQ5+zgI7Q8tDCZZLlEzah6v2orn2t/qQIXFEarOJ3vuQrYL05oVN4wclTx52/dk5x1lBBRcI4j1gxzD3bzI1f0Zw8m/WOj+2emXO8hGnpDaD4PZjXlzEEdFOxMYr2er8O4zpOSMSJv3D4VXW7WnJMBC0smpPsrssxme5VEgZWMShsPqSCy9ibSicMhmyl5uU8b76trF8GnrXYFJjJl1S6JV8kzMfd0l4WLp9MLOlSascLX5ofIYMwHwkTOFEvTgFbgnvufjq+ymLjp11n1V4NwrQRW3b/EVsmznB7tKLvIRDAO2qHx1mpCzT+GVuA60qjWfz2UjN2LR6ZHDJULu8kKfjdIope3PW2uMQks8FiUyoiayOS27qyYmfMzj6XiNbLAc08TMD7xvO7DXfzCuqPfRbTD5QLA2hBtQAclhirX3Oj3yJyjMuGx1xjlKLodkoANnDm5Q0D9ZUOz3/vzuQPRZ5n7wHK0idREhFtF/ykrltl2KyApjjep X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 89ecf06e-e054-4166-8e81-08db7552ee49 X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB9080.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jun 2023 08:05:25.0218 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: F0Qn4cM/fNOjqn85sBzGt1RyuiM9GtMJhz7eaA+lZEROwEosuUU9ukQSTXGDdKebt6KwCa8MRXAKrUtH4f6D6A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB9279 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: "Guoniu.zhou" Abstract gasket operation and driver should implement them for SoC which support gasket. i.MX93 use a different gasket which has different register definition compared with i.MX8. Hence implement the gasket callbacks in order to add ISI support for i.MX93 SoC. Signed-off-by: Guoniu.zhou --- .../media/platform/nxp/imx-isi/imx-isi-core.c | 110 ++++++++++++++++++ .../media/platform/nxp/imx-isi/imx-isi-core.h | 33 ++++++ .../platform/nxp/imx-isi/imx-isi-crossbar.c | 51 ++++---- 3 files changed, 169 insertions(+), 25 deletions(-) diff --git a/drivers/media/platform/nxp/imx-isi/imx-isi-core.c b/drivers/media/platform/nxp/imx-isi/imx-isi-core.c index cd5678139ddf..1fc0d2a67042 100644 --- a/drivers/media/platform/nxp/imx-isi/imx-isi-core.c +++ b/drivers/media/platform/nxp/imx-isi/imx-isi-core.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -279,6 +280,54 @@ static const struct clk_bulk_data mxc_imx8mn_clks[] = { { .id = "apb" }, }; +static int mxc_imx8_gasket_config(struct mxc_isi_dev *isi, + const struct v4l2_mbus_frame_desc *fd, + const struct v4l2_mbus_framefmt *fmt, + const unsigned int port) +{ + u32 val; + + regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_HSIZE, fmt->width); + regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_VSIZE, fmt->height); + + val = GASKET_CTRL_DATA_TYPE(fd->entry[0].bus.csi2.dt); + if (fd->entry[0].bus.csi2.dt == MIPI_CSI2_DT_YUV422_8B) + val |= GASKET_CTRL_DUAL_COMP_ENABLE; + + regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_CTRL, val); + + dev_dbg(isi->dev, "w/h=(%d, %d), data type=0x%x\n", + fmt->width, fmt->height, + fd->entry[0].bus.csi2.dt); + + return 0; +} + +static int mxc_imx8_gasket_enable(struct mxc_isi_dev *isi, + const unsigned int port) +{ + u32 val; + + regmap_read(isi->gasket, GASKET_BASE(port), &val); + val |= GASKET_CTRL_ENABLE; + + regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_CTRL, val); + + return 0; +} + +static void mxc_imx8_gasket_disable(struct mxc_isi_dev *isi, + const unsigned int port) +{ + regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_CTRL, 0); +} + +static const struct mxc_gasket_ops mxc_imx8_gasket_ops = { + .config = mxc_imx8_gasket_config, + .enable = mxc_imx8_gasket_enable, + .disable = mxc_imx8_gasket_disable, +}; + static const struct mxc_isi_plat_data mxc_imx8mn_data = { .model = MXC_ISI_IMX8MN, .num_ports = 1, @@ -290,6 +339,7 @@ static const struct mxc_isi_plat_data mxc_imx8mn_data = { .num_clks = ARRAY_SIZE(mxc_imx8mn_clks), .buf_active_reverse = false, .has_gasket = true, + .gasket_ops = &mxc_imx8_gasket_ops, .has_36bit_dma = false, }; @@ -304,6 +354,65 @@ static const struct mxc_isi_plat_data mxc_imx8mp_data = { .num_clks = ARRAY_SIZE(mxc_imx8mn_clks), .buf_active_reverse = true, .has_gasket = true, + .gasket_ops = &mxc_imx8_gasket_ops, + .has_36bit_dma = true, +}; + +static int mxc_imx93_gasket_config(struct mxc_isi_dev *isi, + const struct v4l2_mbus_frame_desc *fd, + const struct v4l2_mbus_framefmt *fmt, + const unsigned int port) +{ + u32 val; + + val = DISP_MIX_CAMERA_MUX_DATA_TYPE(fd->entry[0].bus.csi2.dt); + regmap_write(isi->gasket, DISP_MIX_CAMERA_MUX, val); + + dev_dbg(isi->dev, "data type=0x%x\n", fd->entry[0].bus.csi2.dt); + + return 0; +} + +static int mxc_imx93_gasket_enable(struct mxc_isi_dev *isi, + const unsigned int port) +{ + u32 val; + + regmap_read(isi->gasket, DISP_MIX_CAMERA_MUX, &val); + val |= DISP_MIX_CAMERA_MUX_GASKET_ENABLE; + regmap_write(isi->gasket, DISP_MIX_CAMERA_MUX, val); + + return 0; +} + +static void mxc_imx93_gasket_disable(struct mxc_isi_dev *isi, + unsigned int port) +{ + u32 val; + + regmap_read(isi->gasket, DISP_MIX_CAMERA_MUX, &val); + val &= ~DISP_MIX_CAMERA_MUX_GASKET_ENABLE; + regmap_write(isi->gasket, DISP_MIX_CAMERA_MUX, val); +} + +static const struct mxc_gasket_ops mxc_imx93_gasket_ops = { + .config = mxc_imx93_gasket_config, + .enable = mxc_imx93_gasket_enable, + .disable = mxc_imx93_gasket_disable, +}; + +static const struct mxc_isi_plat_data mxc_imx93_data = { + .model = MXC_ISI_IMX93, + .num_ports = 1, + .num_channels = 1, + .reg_offset = 0, + .ier_reg = &mxc_imx8_isi_ier_v2, + .set_thd = &mxc_imx8_isi_thd_v1, + .clks = mxc_imx8mn_clks, + .num_clks = ARRAY_SIZE(mxc_imx8mn_clks), + .buf_active_reverse = true, + .has_gasket = true, + .gasket_ops = &mxc_imx93_gasket_ops, .has_36bit_dma = true, }; @@ -518,6 +627,7 @@ static int mxc_isi_remove(struct platform_device *pdev) static const struct of_device_id mxc_isi_of_match[] = { { .compatible = "fsl,imx8mn-isi", .data = &mxc_imx8mn_data }, { .compatible = "fsl,imx8mp-isi", .data = &mxc_imx8mp_data }, + { .compatible = "fsl,imx93-isi", .data = &mxc_imx93_data }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, mxc_isi_of_match); diff --git a/drivers/media/platform/nxp/imx-isi/imx-isi-core.h b/drivers/media/platform/nxp/imx-isi/imx-isi-core.h index 2cb0caf44c42..bbe939e91850 100644 --- a/drivers/media/platform/nxp/imx-isi/imx-isi-core.h +++ b/drivers/media/platform/nxp/imx-isi/imx-isi-core.h @@ -18,6 +18,7 @@ #include #include +#include #include #include #include @@ -59,6 +60,27 @@ struct v4l2_m2m_dev; #define MXC_ISI_M2M "mxc-isi-m2m" #define MXC_MAX_PLANES 3 +/* GASKET (i.MX8MN and i.MX8MP only) */ +#define GASKET_BASE(n) (0x0060 + (n) * 0x30) + +#define GASKET_CTRL 0x0000 +#define GASKET_CTRL_DATA_TYPE(dt) ((dt) << 8) +#define GASKET_CTRL_DATA_TYPE_MASK (0x3f << 8) +#define GASKET_CTRL_DUAL_COMP_ENABLE BIT(1) +#define GASKET_CTRL_ENABLE BIT(0) + +#define GASKET_HSIZE 0x0004 +#define GASKET_VSIZE 0x0008 + +/* dispmix_GPR register (i.MX93 only) */ +#define DISP_MIX_CAMERA_MUX 0x30 +#define DISP_MIX_CAMERA_MUX_DATA_TYPE(x) (((x) & 0x3f) << 3) +#define DISP_MIX_CAMERA_MUX_GASKET_ENABLE BIT(16) + +#define DISP_MIX_CSI_REG 0x48 +#define DISP_MIX_CSI_REG_CFGFREQRANGE(x) ((x) & 0x3f) +#define DISP_MIX_CSI_REG_HSFREQRANGE(x) (((x) & 0x7f) << 8) + struct mxc_isi_dev; struct mxc_isi_m2m_ctx; @@ -147,9 +169,19 @@ struct mxc_isi_set_thd { struct mxc_isi_panic_thd panic_set_thd_v; }; +struct mxc_gasket_ops { + int (*enable)(struct mxc_isi_dev *isi, const unsigned int port); + int (*config)(struct mxc_isi_dev *isi, + const struct v4l2_mbus_frame_desc *fd, + const struct v4l2_mbus_framefmt *fmt, + const unsigned int port); + void (*disable)(struct mxc_isi_dev *isi, const unsigned int port); +}; + enum model { MXC_ISI_IMX8MN, MXC_ISI_IMX8MP, + MXC_ISI_IMX93, }; struct mxc_isi_plat_data { @@ -160,6 +192,7 @@ struct mxc_isi_plat_data { const struct mxc_isi_ier_reg *ier_reg; const struct mxc_isi_set_thd *set_thd; const struct clk_bulk_data *clks; + const struct mxc_gasket_ops *gasket_ops; unsigned int num_clks; bool buf_active_reverse; bool has_gasket; diff --git a/drivers/media/platform/nxp/imx-isi/imx-isi-crossbar.c b/drivers/media/platform/nxp/imx-isi/imx-isi-crossbar.c index f3e3ed080b07..f3b49ff132d4 100644 --- a/drivers/media/platform/nxp/imx-isi/imx-isi-crossbar.c +++ b/drivers/media/platform/nxp/imx-isi/imx-isi-crossbar.c @@ -25,20 +25,6 @@ static inline struct mxc_isi_crossbar *to_isi_crossbar(struct v4l2_subdev *sd) return container_of(sd, struct mxc_isi_crossbar, sd); } -/* ----------------------------------------------------------------------------- - * Media block control (i.MX8MN and i.MX8MP only) - */ -#define GASKET_BASE(n) (0x0060 + (n) * 0x30) - -#define GASKET_CTRL 0x0000 -#define GASKET_CTRL_DATA_TYPE(dt) ((dt) << 8) -#define GASKET_CTRL_DATA_TYPE_MASK (0x3f << 8) -#define GASKET_CTRL_DUAL_COMP_ENABLE BIT(1) -#define GASKET_CTRL_ENABLE BIT(0) - -#define GASKET_HSIZE 0x0004 -#define GASKET_VSIZE 0x0008 - static int mxc_isi_crossbar_gasket_enable(struct mxc_isi_crossbar *xbar, struct v4l2_subdev_state *state, struct v4l2_subdev *remote_sd, @@ -46,13 +32,16 @@ static int mxc_isi_crossbar_gasket_enable(struct mxc_isi_crossbar *xbar, { struct mxc_isi_dev *isi = xbar->isi; const struct v4l2_mbus_framefmt *fmt; + const struct mxc_gasket_ops *gasket_ops = NULL; struct v4l2_mbus_frame_desc fd; - u32 val; int ret; if (!isi->pdata->has_gasket) return 0; + if (isi->pdata->gasket_ops) + gasket_ops = isi->pdata->gasket_ops; + /* * Configure and enable the gasket with the frame size and CSI-2 data * type. For YUV422 8-bit, enable dual component mode unconditionally, @@ -77,16 +66,23 @@ static int mxc_isi_crossbar_gasket_enable(struct mxc_isi_crossbar *xbar, if (!fmt) return -EINVAL; - regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_HSIZE, fmt->width); - regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_VSIZE, fmt->height); - - val = GASKET_CTRL_DATA_TYPE(fd.entry[0].bus.csi2.dt) - | GASKET_CTRL_ENABLE; - - if (fd.entry[0].bus.csi2.dt == MIPI_CSI2_DT_YUV422_8B) - val |= GASKET_CTRL_DUAL_COMP_ENABLE; + if (gasket_ops && gasket_ops->config) { + ret = gasket_ops->config(isi, &fd, fmt, port); + if (ret) { + dev_err(isi->dev, + "failed to configure gasket%d\n", port); + return ret; + } + } - regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_CTRL, val); + if (gasket_ops && gasket_ops->enable) { + ret = gasket_ops->enable(isi, port); + if (ret) { + dev_err(isi->dev, + "failed to enable gasket%d\n", port); + return ret; + } + } return 0; } @@ -95,11 +91,16 @@ static void mxc_isi_crossbar_gasket_disable(struct mxc_isi_crossbar *xbar, unsigned int port) { struct mxc_isi_dev *isi = xbar->isi; + const struct mxc_gasket_ops *gasket_ops = NULL; if (!isi->pdata->has_gasket) return; - regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_CTRL, 0); + if (isi->pdata->gasket_ops) + gasket_ops = isi->pdata->gasket_ops; + + if (gasket_ops && gasket_ops->disable) + gasket_ops->disable(isi, port); } /* -----------------------------------------------------------------------------