From patchwork Tue Mar 5 12:36:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shreeya Patel X-Patchwork-Id: 13582367 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CCC97E767; Tue, 5 Mar 2024 12:38:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709642301; cv=none; b=Iis5qMzvK3mojYe1Bx4eDJHR//YjS7sCbF4Obx5hNQhTqbeM2Rtmir0Vcw8quFRwnIfsYQjcxV5B5YAqXsfKr+7kveOMKgC8Z5VXCeCY6xklW/Zok4gGmlpC6NXeY07CAXv6HU8iugzxh0rBFw2Tkfuw3eE4XGH5vXLcoK5/I5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709642301; c=relaxed/simple; bh=j5sFz/x7pDrucyegTXWXLmPAspnfRkZd5VzxKWDnZ+M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=I0h7dPfJgmntc4ehShTrn/LYz1LWM3t+VakftGZrQ2cTmanc2jq6Iui4wPwkWMnYx5eSEXCqjlyEB/e3d29nA+RuBWRbNK/+EVhFbX54oGhKWoCwyXwgqO60K+3L2rRFCxBTBD8DWqjqS0JgDb1cO8S8LPy6EpWaIDnjZVb4rG4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=SuzrFgpT; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="SuzrFgpT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1709642297; bh=j5sFz/x7pDrucyegTXWXLmPAspnfRkZd5VzxKWDnZ+M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SuzrFgpTBLEDpcob4+cPtEtrvpgkTfYG1XH7LatyuCsWctRFYCMvEr69p4VsYhFKz VRPgUu57m7B1p1pIPImPEFa+xk8W81BqjbtCe0EDcOiIWNHtwMvRoRITAgz3zEizET bChnzW3+FMwQeJd+UNdNjpweyN9iv9GwOdqu7lb8JRQamCXrDuN3+il/7cWhS+C8b+ Zi9hwHb7TFbsU2ZBe2Tr6vtecDJYtZ9agCufbPgS1l7kWOWoyt8DShy/FerPsDg0sC 9C8JAr5J9yJvD74tQKX6XZygvpt4H9j88qh4ktm4jwEfPh29RFT+JTlWOK9x3cPgOv fp43homqYYxCQ== Received: from shreeya.shreeya (ec2-34-240-57-77.eu-west-1.compute.amazonaws.com [34.240.57.77]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: shreeya) by madrid.collaboradmins.com (Postfix) with ESMTPSA id B254B378020D; Tue, 5 Mar 2024 12:38:09 +0000 (UTC) From: Shreeya Patel To: heiko@sntech.de, mchehab@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, jose.abreu@synopsys.com, nelson.costa@synopsys.com, dmitry.osipenko@collabora.com, sebastian.reichel@collabora.com, shawn.wen@rock-chips.com, nicolas.dufresne@collabora.com, hverkuil@xs4all.nl, hverkuil-cisco@xs4all.nl Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm@lists.infradead.org, Shreeya Patel Subject: [PATCH v2 3/6] dt-bindings: media: Document HDMI RX Controller Date: Tue, 5 Mar 2024 18:06:45 +0530 Message-Id: <20240305123648.8847-4-shreeya.patel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240305123648.8847-1-shreeya.patel@collabora.com> References: <20240305123648.8847-1-shreeya.patel@collabora.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document bindings for the Synopsys DesignWare HDMI RX Controller. Reviewed-by: Dmitry Osipenko Signed-off-by: Shreeya Patel Reviewed-by: Rob Herring --- Changes in v2 :- - Add a description for the hardware - Rename resets, vo1 grf and HPD properties - Add a proper description for grf and vo1-grf phandles - Rename the HDMI Input node name to hdmi-receiver - Improve the subject line - Include gpio header file in example to fix dt_binding_check failure .../bindings/media/snps,dw-hdmi-rx.yaml | 132 ++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml diff --git a/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml new file mode 100644 index 000000000000..ea9f728c11b3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Device Tree bindings for Synopsys DesignWare HDMI RX Controller + +--- +$id: http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare HDMI RX Controller + +maintainers: + - Shreeya Patel + +description: + Synopsys DesignWare HDMI Input Controller preset on RK3588 SoCs + allowing devices to receive and decode high-resolution video streams + from external sources like media players, cameras, laptops, etc. + +properties: + compatible: + items: + - const: rockchip,rk3588-hdmirx-ctrler + - const: snps,dw-hdmi-rx + + reg: + maxItems: 1 + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: cec + - const: hdmi + - const: dma + + clocks: + maxItems: 7 + + clock-names: + items: + - const: aclk + - const: audio + - const: cr_para + - const: pclk + - const: ref + - const: hclk_s_hdmirx + - const: hclk_vo1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 4 + + reset-names: + items: + - const: axi + - const: apb + - const: ref + - const: biu + + memory-region: + maxItems: 1 + + hpd-gpios: + description: GPIO specifier for HPD. + maxItems: 1 + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the general register file + containing HDMIRX PHY status bits. + + rockchip,vo1-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the Video Output GRF register + to enable EDID transfer through SDAIN and SCLIN. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - pinctrl-0 + - hpd-gpios + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + hdmi_receiver: hdmi-receiver@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; + reg = <0xfdee0000 0x6000>; + interrupts = , + , + ; + interrupt-names = "cec", "hdmi", "dma"; + clocks = <&cru ACLK_HDMIRX>, + <&cru CLK_HDMIRX_AUD>, + <&cru CLK_CR_PARA>, + <&cru PCLK_HDMIRX>, + <&cru CLK_HDMIRX_REF>, + <&cru PCLK_S_HDMIRX>, + <&cru HCLK_VO1>; + clock-names = "aclk", + "audio", + "cr_para", + "pclk", + "ref", + "hclk_s_hdmirx", + "hclk_vo1"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, + <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; + reset-names = "axi", "apb", "ref", "biu"; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_detection>; + pinctrl-names = "default"; + memory-region = <&hdmirx_cma>; + hpd-gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + };