From patchwork Wed Mar 27 13:41:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Link Mauve X-Patchwork-Id: 13606703 Received: from luna.linkmauve.fr (luna.linkmauve.fr [82.65.109.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8889413E6AA; Wed, 27 Mar 2024 13:41:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=82.65.109.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711546882; cv=none; b=Biuw2eCSqhRWu2ab+9qjRG5z9j/K6t4TDmzHBoNhS4HCz7Mbq68qb+MI71wdbYXy3mu6oZpK4ali6SzmXS7hJiOqmh+LQSvBVcFOVf4PswKKcmli8sQErMc/r3RERBgRHBF1IzfHtkr88ZDTeouchBkuGirlpHjWPwIeAnKzI2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711546882; c=relaxed/simple; bh=E0uEtYtvt7IbkwldYNcvOykBcdKHQTNNscgS3IBN8Vs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BTo5iRiIPnP1Biopy5IX2d4R9L/LJPGaWSbiyuTryo1c1pEO0hHRQw9GFxOLjYghrT8Aalyx5WLCY5oEftDbfj7bbc5rrXbyp3gBpxI9LzqFO3LTmxRm1fTxsG3ccSobA94qlL05BJuyTz9UcMqqCYRNswGxqNM89NqscC7Ii1M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=linkmauve.fr; spf=pass smtp.mailfrom=linkmauve.fr; arc=none smtp.client-ip=82.65.109.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=linkmauve.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linkmauve.fr Received: by luna.linkmauve.fr (Postfix, from userid 1000) id DCE50101AF3A; Wed, 27 Mar 2024 14:41:18 +0100 (CET) From: Emmanuel Gil Peyrot To: linux-kernel@vger.kernel.org Cc: Emmanuel Gil Peyrot , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Joerg Roedel , Will Deacon , Robin Murphy , Sebastian Reichel , Cristian Ciocaltea , Dragan Simic , Shreeya Patel , Chris Morgan , Andy Yan , Nicolas Frattaroli , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Subject: [PATCH v2 2/2] arm64: dts: rockchip: Add VEPU121 to rk3588 Date: Wed, 27 Mar 2024 14:41:12 +0100 Message-ID: <20240327134115.424846-3-linkmauve@linkmauve.fr> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240327134115.424846-1-linkmauve@linkmauve.fr> References: <20240327134115.424846-1-linkmauve@linkmauve.fr> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The TRM (version 1.0 page 385) lists five VEPU121 cores, but only four interrupts are listed (on page 24), so I’ve only enabled four of them for now. Signed-off-by: Emmanuel Gil Peyrot Reviewed-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 +++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 87b83c87bd55..510ed3db9d01 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -2488,6 +2488,86 @@ gpio4: gpio@fec50000 { }; }; + jpeg_enc0: video-codec@fdba0000 { + compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu"; + reg = <0x0 0xfdba0000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; + clock-names = "aclk", "hclk"; + iommus = <&jpeg_enc0_mmu>; + power-domains = <&power RK3588_PD_VDPU>; + }; + + jpeg_enc0_mmu: iommu@fdba0800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdba0800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + }; + + jpeg_enc1: video-codec@fdba4000 { + compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu"; + reg = <0x0 0xfdba4000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; + clock-names = "aclk", "hclk"; + iommus = <&jpeg_enc1_mmu>; + power-domains = <&power RK3588_PD_VDPU>; + }; + + jpeg_enc1_mmu: iommu@fdba4800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdba4800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + }; + + jpeg_enc2: video-codec@fdba8000 { + compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu"; + reg = <0x0 0xfdba8000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; + clock-names = "aclk", "hclk"; + iommus = <&jpeg_enc2_mmu>; + power-domains = <&power RK3588_PD_VDPU>; + }; + + jpeg_enc2_mmu: iommu@fdba8800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdba8800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + }; + + jpeg_enc3: video-codec@fdbac000 { + compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu"; + reg = <0x0 0xfdbac000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; + clock-names = "aclk", "hclk"; + iommus = <&jpeg_enc3_mmu>; + power-domains = <&power RK3588_PD_VDPU>; + }; + + jpeg_enc3_mmu: iommu@fdbac800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdbac800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + }; + av1d: video-codec@fdc70000 { compatible = "rockchip,rk3588-av1-vpu"; reg = <0x0 0xfdc70000 0x0 0x800>;