From patchwork Tue Aug 13 23:00:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13762673 Received: from mail-qt1-f182.google.com (mail-qt1-f182.google.com [209.85.160.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 804031A7058; Tue, 13 Aug 2024 23:00:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723590060; cv=none; b=bErLO4f3WbfgU8vMP20hfAWNHeHL19nX9PfvfvRylQDKuJmEH6w9QW7YZyUGcq/Sg6L0OglT/AjRl90dbRb1QFMshgxO07k6A8rAMt5+9LTvuyauQ8s9qg0Qqszf0ix1TY3RwbojdVbXOPbY78x/e86lrZxsx5A39pwdD6gFv/c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723590060; c=relaxed/simple; bh=MTs+G93svOkXFpMKIGKuRkI2y7ULikZDdTjHwEouAaY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mgwntEDF2mk58E8fhtJMDKbn1tG2nMI/D/wBXEQMFxDLVsvZF7AkBkv2VG2170H3mOBY7fA63jAWmvtNhNK9vh9kuA1qUpucjGI/MRl/nDqypZAOrGUwuI/JKdj6BdQ9FqjP/ENN1ofKKdkBmPgRw7DtyzBOKsPUkWEZzBpcMzs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ESf0qnns; arc=none smtp.client-ip=209.85.160.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ESf0qnns" Received: by mail-qt1-f182.google.com with SMTP id d75a77b69052e-44ff7bdb5a6so32482281cf.3; Tue, 13 Aug 2024 16:00:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1723590057; x=1724194857; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pHbp5xm4kw6fJSSbkDbUTNVhDZ+PJQcOYIRUSidU0PI=; b=ESf0qnnsm0Itp5C3As6R9yQJHGUdI5UrN40t8drM4LHyYQjAhZHjo6ArOnLfpFHFzL wSyTal5CO04HPh5jQ9NC2LnAZatkkSypbXYVe4q7lBJ4m80eGVz5Q9YXxiQncfOO4dl9 NWzYh6uvWqh8AEwv9sHuXCE3EWZVAxff3cZHJYO8SEs+ybS6DO9hI0rc9Y9POxwW2ZGI yft4Lbp6jVV6d+f2VtnAJRDgIOynkOy6AZhcGbicvNSSXjE9FMIF16iXwbR5AEC+j5Vx 4pb1jE8yqtZeWTyqDi0LbvM1m8f0vNoh0NBUKIJzNoqNVkVr/pnAcW9SHlfLQ1hJMExQ yTTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723590057; x=1724194857; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pHbp5xm4kw6fJSSbkDbUTNVhDZ+PJQcOYIRUSidU0PI=; b=Ihqyixf7EysZkHnWZGiV008HOJ+WBqKtiC9APTa+P335dNBA253UToPMaWUVU7RM0V KUGh4Ed4dRgnj9fn/FbJ1CHpstJiCCW3drnc8hNx8BXdSExGmXmBNuQ8jgcHpTU6Hjgc NhEKTt9+A3gtllTq18ffnJUwdGg87gBqzqaf2IBIONwPLeIu+W4BWI1tPCi4FAra0xP4 HtWFZZd9jkNLl3VzuRHCZZRn9q9UqtF+2NYeiBZixhV1elzHEeetPBUYkJCMQ84tYWKJ 9OiC5MoZx9txsTajfAkyFIj/QsOSawo4iGAvQTbXIEWoVxf5DZ3MlNryozM/wHIpN2q4 44xw== X-Forwarded-Encrypted: i=1; AJvYcCUj/Urt/Y2S+VIA2xKh36ea+Tvi2FtPOXlJq4W9mez8Eo267OYVKnDLPOASGEZof7sGOPPouNLyHIWCV3H+lXWhjK+uOrN1IExOjabrfYwA6i/XB97WeoN9/ESE1I3PVK90O3R9CU4xXyuLjBL421eS1+HrvcuQLV43HOppLnDiYuAdjKbpeQpgxK7qE4DUvDEU8zAfwjzBEjakihpPEjLeMA== X-Gm-Message-State: AOJu0Yz8Cxyu4wHL3MUxrP7wWTl/h6x/oADq8zzKePIgMgaHNEAoPIw3 CWT2HT9OE0AguaUiA6MRrmIiNvRVFDJ16Xvml+mpEaRzOlxJcvpt X-Google-Smtp-Source: AGHT+IG12o+DDxSng9qqTCcj3SZsCQqnBjgOGSw2xrsJ9Pal5e9/kUrGXQ9++z6UsWm9oV1Si1fJaw== X-Received: by 2002:a05:622a:1f05:b0:447:e1a4:6c9e with SMTP id d75a77b69052e-4535ba8c5e8mr8947451cf.16.1723590057226; Tue, 13 Aug 2024 16:00:57 -0700 (PDT) Received: from localhost ([2607:fea8:52a3:d200:324c:b818:b179:79b]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4531c1dc4bdsm35969621cf.51.2024.08.13.16.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Aug 2024 16:00:56 -0700 (PDT) From: Richard Acayan To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , "Bryan O'Donoghue" , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-media@vger.kernel.org Cc: Richard Acayan Subject: [PATCH v2 5/5] arm64: dts: qcom: sdm670: add camss and cci Date: Tue, 13 Aug 2024 19:00:44 -0400 Message-ID: <20240813230037.84004-13-mailingradian@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240813230037.84004-8-mailingradian@gmail.com> References: <20240813230037.84004-8-mailingradian@gmail.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the camera subsystem and CCI used to interface with cameras on the Snapdragon 670. Signed-off-by: Richard Acayan --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 193 +++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index ba93cef33dbb..63a956e0f55f 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2022, Richard Acayan. All rights reserved. */ +#include #include #include #include @@ -1168,6 +1169,34 @@ tlmm: pinctrl@3400000 { gpio-ranges = <&tlmm 0 0 151>; wakeup-parent = <&pdc>; + cci0_default: cci0-default-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_sleep: cci0-sleep-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_default: cci1-default-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_sleep: cci1-sleep-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + qup_i2c0_default: qup-i2c0-default-state { pins = "gpio0", "gpio1"; function = "qup0"; @@ -1400,6 +1429,170 @@ spmi_bus: spmi@c440000 { #interrupt-cells = <4>; }; + cci: cci@ac4a000 { + compatible = "qcom,sdm670-cci", "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4a000 0 0x4000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_CLK>, + <&camcc CAM_CC_CCI_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CCI_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + camss: camera-controller@ac65000 { + compatible = "qcom,sdm670-camss"; + reg = <0 0x0ac65000 0 0x1000>, + <0 0x0ac66000 0 0x1000>, + <0 0x0ac67000 0 0x1000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb3000 0 0x1000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acc4000 0 0x4000>, + <0 0x0acc8000 0 0x1000>; + reg-names = "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "csid0", + "vfe1", + "csid1", + "vfe_lite", + "csid2"; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csi0", + "csi1", + "csi2", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe_lite", + "vfe_lite_cphy_rx"; + + iommus = <&apps_smmu 0x808 0x0>, + <&apps_smmu 0x810 0x8>, + <&apps_smmu 0xc08 0x0>, + <&apps_smmu 0xc10 0x8>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + camss_port0: port@0 { + reg = <0>; + }; + + camss_port1: port@1 { + reg = <1>; + }; + + camss_port2: port@2 { + reg = <2>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sdm845-camcc"; reg = <0 0x0ad00000 0 0x10000>;