@@ -2225,7 +2225,7 @@ The following table list existing packed 48bit wide RGB formats.
\endgroup
On LVDS buses, usually each sample is transferred serialized in seven
-time slots per pixel clock, on three (18-bit) or four (24-bit)
+time slots per pixel clock, on three (18-bit) or four (24-bit) or five (30-bit)
differential data pairs at the same time. The remaining bits are used
for control signals as defined by SPWG/PSWG/VESA or JEIDA standards. The
24-bit RGB format serialized in seven time slots on four lanes using
@@ -2246,11 +2246,12 @@ JEIDA defined bit mapping will be named
- Code
-
-
- - :cspan:`3` Data organization
+ - :cspan:`4` Data organization
* -
-
- Timeslot
- Lane
+ - 4
- 3
- 2
- 1
@@ -2262,6 +2263,7 @@ JEIDA defined bit mapping will be named
- 0
-
-
+ -
- d
- b\ :sub:`1`
- g\ :sub:`0`
@@ -2270,6 +2272,7 @@ JEIDA defined bit mapping will be named
- 1
-
-
+ -
- d
- b\ :sub:`0`
- r\ :sub:`5`
@@ -2278,6 +2281,7 @@ JEIDA defined bit mapping will be named
- 2
-
-
+ -
- d
- g\ :sub:`5`
- r\ :sub:`4`
@@ -2286,6 +2290,7 @@ JEIDA defined bit mapping will be named
- 3
-
-
+ -
- b\ :sub:`5`
- g\ :sub:`4`
- r\ :sub:`3`
@@ -2294,6 +2299,7 @@ JEIDA defined bit mapping will be named
- 4
-
-
+ -
- b\ :sub:`4`
- g\ :sub:`3`
- r\ :sub:`2`
@@ -2302,6 +2308,7 @@ JEIDA defined bit mapping will be named
- 5
-
-
+ -
- b\ :sub:`3`
- g\ :sub:`2`
- r\ :sub:`1`
@@ -2310,6 +2317,7 @@ JEIDA defined bit mapping will be named
- 6
-
-
+ -
- b\ :sub:`2`
- g\ :sub:`1`
- r\ :sub:`0`
@@ -2319,6 +2327,7 @@ JEIDA defined bit mapping will be named
- 0x1011
- 0
-
+ -
- d
- d
- b\ :sub:`1`
@@ -2327,6 +2336,7 @@ JEIDA defined bit mapping will be named
-
- 1
-
+ -
- b\ :sub:`7`
- d
- b\ :sub:`0`
@@ -2335,6 +2345,7 @@ JEIDA defined bit mapping will be named
-
- 2
-
+ -
- b\ :sub:`6`
- d
- g\ :sub:`5`
@@ -2343,6 +2354,7 @@ JEIDA defined bit mapping will be named
-
- 3
-
+ -
- g\ :sub:`7`
- b\ :sub:`5`
- g\ :sub:`4`
@@ -2351,6 +2363,7 @@ JEIDA defined bit mapping will be named
-
- 4
-
+ -
- g\ :sub:`6`
- b\ :sub:`4`
- g\ :sub:`3`
@@ -2359,6 +2372,7 @@ JEIDA defined bit mapping will be named
-
- 5
-
+ -
- r\ :sub:`7`
- b\ :sub:`3`
- g\ :sub:`2`
@@ -2367,6 +2381,7 @@ JEIDA defined bit mapping will be named
-
- 6
-
+ -
- r\ :sub:`6`
- b\ :sub:`2`
- g\ :sub:`1`
@@ -2377,6 +2392,7 @@ JEIDA defined bit mapping will be named
- 0x1012
- 0
-
+ -
- d
- d
- b\ :sub:`3`
@@ -2385,6 +2401,7 @@ JEIDA defined bit mapping will be named
-
- 1
-
+ -
- b\ :sub:`1`
- d
- b\ :sub:`2`
@@ -2393,6 +2410,7 @@ JEIDA defined bit mapping will be named
-
- 2
-
+ -
- b\ :sub:`0`
- d
- g\ :sub:`7`
@@ -2401,6 +2419,7 @@ JEIDA defined bit mapping will be named
-
- 3
-
+ -
- g\ :sub:`1`
- b\ :sub:`7`
- g\ :sub:`6`
@@ -2409,6 +2428,7 @@ JEIDA defined bit mapping will be named
-
- 4
-
+ -
- g\ :sub:`0`
- b\ :sub:`6`
- g\ :sub:`5`
@@ -2417,6 +2437,7 @@ JEIDA defined bit mapping will be named
-
- 5
-
+ -
- r\ :sub:`1`
- b\ :sub:`5`
- g\ :sub:`4`
@@ -2425,10 +2446,141 @@ JEIDA defined bit mapping will be named
-
- 6
-
+ -
+ - r\ :sub:`0`
+ - b\ :sub:`4`
+ - g\ :sub:`3`
+ - r\ :sub:`2`
+ * .. _MEDIA-BUS-FMT-RGB101010-1X7X5-SPWG:
+
+ - MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG
+ - 0x1026
+ - 0
+ -
+ - d
+ - d
+ - d
+ - b\ :sub:`1`
+ - g\ :sub:`0`
+ * -
+ -
+ - 1
+ -
+ - b\ :sub:`9`
+ - b\ :sub:`7`
+ - d
+ - b\ :sub:`0`
+ - r\ :sub:`5`
+ * -
+ -
+ - 2
+ -
+ - b\ :sub:`8`
+ - b\ :sub:`6`
+ - d
+ - g\ :sub:`5`
+ - r\ :sub:`4`
+ * -
+ -
+ - 3
+ -
+ - g\ :sub:`9`
+ - g\ :sub:`7`
+ - b\ :sub:`5`
+ - g\ :sub:`4`
+ - r\ :sub:`3`
+ * -
+ -
+ - 4
+ -
+ - g\ :sub:`8`
+ - g\ :sub:`6`
+ - b\ :sub:`4`
+ - g\ :sub:`3`
+ - r\ :sub:`2`
+ * -
+ -
+ - 5
+ -
+ - r\ :sub:`9`
+ - r\ :sub:`7`
+ - b\ :sub:`3`
+ - g\ :sub:`2`
+ - r\ :sub:`1`
+ * -
+ -
+ - 6
+ -
+ - r\ :sub:`8`
+ - r\ :sub:`6`
+ - b\ :sub:`2`
+ - g\ :sub:`1`
- r\ :sub:`0`
+ * .. _MEDIA-BUS-FMT-RGB101010-1X7X5-JEIDA:
+
+ - MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA
+ - 0x1027
+ - 0
+ -
+ - d
+ - d
+ - d
+ - b\ :sub:`5`
+ - g\ :sub:`4`
+ * -
+ -
+ - 1
+ -
+ - b\ :sub:`1`
+ - b\ :sub:`3`
+ - d
- b\ :sub:`4`
+ - r\ :sub:`9`
+ * -
+ -
+ - 2
+ -
+ - b\ :sub:`0`
+ - b\ :sub:`2`
+ - d
+ - g\ :sub:`9`
+ - r\ :sub:`8`
+ * -
+ -
+ - 3
+ -
+ - g\ :sub:`1`
- g\ :sub:`3`
+ - b\ :sub:`9`
+ - g\ :sub:`8`
+ - r\ :sub:`7`
+ * -
+ -
+ - 4
+ -
+ - g\ :sub:`0`
+ - g\ :sub:`2`
+ - b\ :sub:`8`
+ - g\ :sub:`7`
+ - r\ :sub:`6`
+ * -
+ -
+ - 5
+ -
+ - r\ :sub:`1`
+ - r\ :sub:`3`
+ - b\ :sub:`7`
+ - g\ :sub:`6`
+ - r\ :sub:`5`
+ * -
+ -
+ - 6
+ -
+ - r\ :sub:`0`
- r\ :sub:`2`
+ - b\ :sub:`6`
+ - g\ :sub:`5`
+ - r\ :sub:`4`
.. raw:: latex
@@ -34,7 +34,7 @@
#define MEDIA_BUS_FMT_FIXED 0x0001
-/* RGB - next is 0x1026 */
+/* RGB - next is 0x1028 */
#define MEDIA_BUS_FMT_RGB444_1X12 0x1016
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
@@ -68,6 +68,8 @@
#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f
#define MEDIA_BUS_FMT_RGB101010_1X30 0x1018
+#define MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG 0x1026
+#define MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA 0x1027
#define MEDIA_BUS_FMT_RGB666_1X36_CPADLO 0x1020
#define MEDIA_BUS_FMT_RGB888_1X36_CPADLO 0x1021
#define MEDIA_BUS_FMT_RGB121212_1X36 0x1019
Add two media bus formats that identify 30-bit RGB pixels transmitted by a LVDS link with five differential data pairs, serialized into 7 time slots, using standard SPWG/VESA or JEIDA data mapping. Signed-off-by: Liu Ying <victor.liu@nxp.com> --- v3: * New patch. .../media/v4l/subdev-formats.rst | 156 +++++++++++++++++- include/uapi/linux/media-bus-format.h | 4 +- 2 files changed, 157 insertions(+), 3 deletions(-)