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Thu, 13 Mar 2025 18:43:37 +0000 (UTC) Received: from shalem.redhat.com (unknown [10.45.224.5]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 898CF300377A; Thu, 13 Mar 2025 18:43:34 +0000 (UTC) From: Hans de Goede To: Sakari Ailus , Heimir Thor Sverrisson Cc: Hans de Goede , Stanislaw Gruszka , Ingvar Hagelund , Joachim Reichel , Bryan O'Donoghue , Hao Yao , Mauro Carvalho Chehab , linux-media@vger.kernel.org Subject: [PATCH v8 05/14] media: ov02c10: link-freq-index and pixel-rate fixes Date: Thu, 13 Mar 2025 19:43:05 +0100 Message-ID: <20250313184314.91410-6-hdegoede@redhat.com> In-Reply-To: <20250313184314.91410-1-hdegoede@redhat.com> References: <20250313184314.91410-1-hdegoede@redhat.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 link-freq-index and pixel-rate fixes: - The link_freq_index is (typically) not mode specific move it from the mode struct to the ov02c10 struct - Having one supported link-freq in bus_cfg.link_frequencies[] is enough switch to v4l2_link_freq_to_bitmap() to only require one match and store the first match in ov02c10->link_freq_index for use when setting up the controls - Use ov02c10->link_freq_index to set the value of the link-freq control - Note the above are no-ops because currently only 1 link-freq is supported - Use link-freq + lane-count to calculate the pixelrate instead of hard- coding it to 80MHz, this corrects the pixel-rate to 160MHz for 2 lanes - The link-freq and pixel-rate are set to a fixed value at probe() time and never change, drop the unnecessary setting of these controls from ov02c10_set_format() Signed-off-by: Hans de Goede --- drivers/media/i2c/ov02c10.c | 52 ++++++++++++++----------------------- 1 file changed, 19 insertions(+), 33 deletions(-) diff --git a/drivers/media/i2c/ov02c10.c b/drivers/media/i2c/ov02c10.c index ad5ab6c8a803..4b1b41f74ca2 100644 --- a/drivers/media/i2c/ov02c10.c +++ b/drivers/media/i2c/ov02c10.c @@ -16,9 +16,7 @@ #include #define OV02C10_LINK_FREQ_400MHZ 400000000ULL -#define OV02C10_SCLK 80000000LL #define OV02C10_MCLK 19200000 -#define OV02C10_DATA_LANES 1 #define OV02C10_RGB_DEPTH 10 #define OV02C10_REG_CHIP_ID CCI_REG16(0x300a) @@ -78,9 +76,6 @@ struct ov02c10_mode { /* Min vertical timining size */ u32 vts_min; - /* Link frequency needed for this resolution */ - u32 link_freq_index; - /* MIPI lanes used */ u8 mipi_lanes; @@ -409,7 +404,8 @@ struct ov02c10 { /* To serialize asynchronous callbacks */ struct mutex mutex; - /* MIPI lanes used */ + /* MIPI lane info */ + u32 link_freq_index; u8 mipi_lanes; /* Streaming on/off */ @@ -506,9 +502,8 @@ static int ov02c10_init_controls(struct ov02c10 *ov02c10) { struct v4l2_ctrl_handler *ctrl_hdlr; const struct ov02c10_mode *cur_mode; - s64 exposure_max, h_blank; + s64 exposure_max, h_blank, pixel_rate; u32 vblank_min, vblank_max, vblank_default; - int size; int ret = 0; ctrl_hdlr = &ov02c10->ctrl_handler; @@ -518,19 +513,22 @@ static int ov02c10_init_controls(struct ov02c10 *ov02c10) ctrl_hdlr->lock = &ov02c10->mutex; cur_mode = ov02c10->cur_mode; - size = ARRAY_SIZE(link_freq_menu_items); ov02c10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_LINK_FREQ, - size - 1, 0, + ov02c10->link_freq_index, 0, link_freq_menu_items); if (ov02c10->link_freq) ov02c10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; + /* MIPI lanes are DDR -> use link-freq * 2 */ + pixel_rate = link_freq_menu_items[ov02c10->link_freq_index] * 2 * + ov02c10->mipi_lanes / OV02C10_RGB_DEPTH; + ov02c10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_PIXEL_RATE, 0, - OV02C10_SCLK, 1, OV02C10_SCLK); + pixel_rate, 1, pixel_rate); vblank_min = cur_mode->vts_min - cur_mode->height; vblank_max = OV02C10_VTS_MAX - cur_mode->height; @@ -801,8 +799,6 @@ static int ov02c10_set_format(struct v4l2_subdev *sd, *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format; } else { ov02c10->cur_mode = mode; - __v4l2_ctrl_s_ctrl(ov02c10->link_freq, mode->link_freq_index); - __v4l2_ctrl_s_ctrl_int64(ov02c10->pixel_rate, OV02C10_SCLK); /* Update limits and set FPS to default */ vblank_def = mode->vts_def - mode->height; @@ -927,9 +923,9 @@ static int ov02c10_check_hwcfg(struct device *dev, struct ov02c10 *ov02c10) }; struct fwnode_handle *ep; struct fwnode_handle *fwnode = dev_fwnode(dev); - unsigned int i, j; - int ret; + unsigned long link_freq_bitmap; u32 ext_clk; + int ret; if (!fwnode) return -ENXIO; @@ -950,26 +946,16 @@ static int ov02c10_check_hwcfg(struct device *dev, struct ov02c10 *ov02c10) if (ret) return ret; - if (!bus_cfg.nr_of_link_frequencies) { - dev_err(dev, "no link frequencies defined"); - ret = -EINVAL; + ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies, + bus_cfg.nr_of_link_frequencies, + link_freq_menu_items, + ARRAY_SIZE(link_freq_menu_items), + &link_freq_bitmap); + if (ret) goto out_err; - } - for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { - for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { - if (link_freq_menu_items[i] == - bus_cfg.link_frequencies[j]) - break; - } - - if (j == bus_cfg.nr_of_link_frequencies) { - dev_err(dev, "no link frequency %lld supported", - link_freq_menu_items[i]); - ret = -EINVAL; - goto out_err; - } - } + /* v4l2_link_freq_to_bitmap() guarantees at least 1 bit is set */ + ov02c10->link_freq_index = ffs(link_freq_bitmap) - 1; if (bus_cfg.bus.mipi_csi2.num_data_lanes != 2 && bus_cfg.bus.mipi_csi2.num_data_lanes != 4) {