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[213.36.7.13]) by smtp.gmail.com with ESMTPSA id t20-20020a05600c199400b0041c012ca327sm7469761wmq.45.2024.04.29.09.21.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Apr 2024 09:21:14 -0700 (PDT) Message-ID: <4ea494cf-134e-4380-aea1-4c166a626561@freebox.fr> Date: Mon, 29 Apr 2024 18:15:37 +0200 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v1 1/3] dt-bindings: media: add qcom,msm8998-venus From: Marc Gonzalez To: Bjorn Andersson , Jeffrey Hugo , Konrad Dybcio , Stanimir Varbanov , Vikash Garodia , Bryan O Donoghue Cc: MSM , linux-media , DT , Pierre-Hugues Husson , Arnaud Vrac , Rob Herring , Krzysztof Kozlowski , Conor Dooley References: <2b21b160-a530-486a-9404-c5bf8863ffed@freebox.fr> Content-Language: en-US In-Reply-To: <2b21b160-a530-486a-9404-c5bf8863ffed@freebox.fr> Add YAML binding for Qualcomm MSM8998 Venus HW video encode and decode. (Based on qcom,msm8996-venus.yaml) Signed-off-by: Marc Gonzalez Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/media/qcom,msm8998-venus.yaml | 155 ++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,msm8998-venus.yaml b/Documentation/devicetree/bindings/media/qcom,msm8998-venus.yaml new file mode 100644 index 0000000000000..86a20954cb354 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,msm8998-venus.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,msm8998-venus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8998 Venus video encode and decode accelerators + +maintainers: + - Stanimir Varbanov + +description: | + The Venus IP is a video encode and decode accelerator present + on Qualcomm platforms + +allOf: + - $ref: qcom,venus-common.yaml# + +properties: + compatible: + const: qcom,msm8998-venus + + power-domains: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: core + - const: iface + - const: bus + - const: mbus + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: video-mem + - const: cpu-cfg + + iommus: + maxItems: 20 + + video-decoder: + type: object + + properties: + compatible: + const: venus-decoder + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + power-domains: + maxItems: 1 + + required: + - compatible + - clocks + - clock-names + - power-domains + + additionalProperties: false + + video-encoder: + type: object + + properties: + compatible: + const: venus-encoder + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + power-domains: + maxItems: 1 + + required: + - compatible + - clocks + - clock-names + - power-domains + + additionalProperties: false + +required: + - compatible + - iommus + - video-decoder + - video-encoder + +unevaluatedProperties: false + +examples: + - | + #include + #include + + video-codec@cc00000 { + compatible = "qcom,msm8998-venus"; + reg = <0x0cc00000 0xff000>; + interrupts = ; + power-domains = <&mmcc VIDEO_TOP_GDSC>; + clocks = <&mmcc VIDEO_CORE_CLK>, + <&mmcc VIDEO_AHB_CLK>, + <&mmcc VIDEO_AXI_CLK>, + <&mmcc VIDEO_MAXI_CLK>; + clock-names = "core", "iface", "bus", "mbus"; + iommus = <&mmss_smmu 0x400>, + <&mmss_smmu 0x401>, + <&mmss_smmu 0x40a>, + <&mmss_smmu 0x407>, + <&mmss_smmu 0x40e>, + <&mmss_smmu 0x40f>, + <&mmss_smmu 0x408>, + <&mmss_smmu 0x409>, + <&mmss_smmu 0x40b>, + <&mmss_smmu 0x40c>, + <&mmss_smmu 0x40d>, + <&mmss_smmu 0x410>, + <&mmss_smmu 0x421>, + <&mmss_smmu 0x428>, + <&mmss_smmu 0x429>, + <&mmss_smmu 0x42b>, + <&mmss_smmu 0x42c>, + <&mmss_smmu 0x42d>, + <&mmss_smmu 0x411>, + <&mmss_smmu 0x431>; + memory-region = <&venus_mem>; + + video-decoder { + compatible = "venus-decoder"; + clocks = <&mmcc VIDEO_SUBCORE0_CLK>; + clock-names = "core"; + power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>; + }; + + video-encoder { + compatible = "venus-encoder"; + clocks = <&mmcc VIDEO_SUBCORE1_CLK>; + clock-names = "core"; + power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>; + }; + };