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Mon, 7 Jun 2021 08:43:32 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 01/13] dt-bindings: media: imx8q: add imx video codec bindings Date: Mon, 7 Jun 2021 16:42:48 +0800 Message-Id: <7cd02157f9a9cc7a773bd02137a92a04077638e5.1623054584.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: X-Originating-IP: [119.31.174.70] X-ClientProxiedBy: SG2PR06CA0203.apcprd06.prod.outlook.com (2603:1096:4:1::35) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SG2PR06CA0203.apcprd06.prod.outlook.com (2603:1096:4:1::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.22 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 6a1ja0yjnwjsqiE0KPnCZtXYqIzckR+1N6/gSGm53027WSRwOxFapQBu/rKtLO12VjD38kHwoJJmsu6LSm+c/di/8s/ydVejLlYKfT4uIhld0ujHcHemQfQ7mQVOH3/1Hgxu6Z5YOscgmr49AdJG4yyj7MKDNTyJpk++EhOF/nJJszCWeV7cXxN2nYINbHVCWf0tx7CpLaRRQ/tsrskExIFSBFi6d9znLwINUMRm35TRvGomUWhXRbX+AuuWTtCX1QRxXUt3MEDxGgNuHRDCrL2JrR9yfUiceGko/bKgSO6H3k4G4LkeapgGSwFO9grA8pll8TanX18/HlKpe2KMn1+fG5R2Hubg2QyQxZSlU7thbfMos4li/afbuN/DU/qftLg2PlFejmzM3W9/Zy2LlslRgp5po+f6S02ykH1tYfWJmhjN3IoDwRRZUlMTuiwsXQXUMA/qMnNi8JRISnI+2MKmTYNulH94j3zGdJhXgCG4PgQK3apdbyAJirG3ZML0Pthgtr7u22UkHVSPxaydsk8KkVnXlA/imWAZPYIVg9KamgZiZHaSBDSKaQPdhJQzALpWcnykLYF0xZpV+q67TtA8OaYu94UPJfsx6sjdec+rNIF6Im36oU0lmNMS+FOTmjivr6LErc2zBAfn3nlwNABaKVerUkiwxXBb05khD84u61pkbl5YKaamgYAPYe/EsVnx4gJPq4PF2wK+Ue7WwAUc0h3/6mSwtehbD4jlxAEEWTGJLX/2eoK2EPmtqc3Ys8io0DN4ChV6Rxm3Zdud0UXqg/4RIlV6DxSbKXc3+gslMD1HKJtD2pEmSNkC91HsoN2JXs6y2jA0Qadu9lB8950TVt9SXa73whuHuKRUfv+oKZdf6aySwOhUuR0eI5eI3pJSKvqRisxVZa1oDsDm/fqITRI1rLtWo5wxmmO8KBAHa2T+yHqXWRXtBz5cfLV5lK7c2faIxZ+NHJDYP0ZAl4TabIloW9tZsibCyJrhVNw0v7FyB3sMjXITUv6w+7hIRU4ox5uASnQA0kqjcbykrB9ubb2MYhyi5cD7eYPopIwJr9pZemQWXdbI7EodJlsPxMKIGryTCWofyR1kwfjDgqtkwUZRDDlfg4iv77ZORLz4vrGPF8tNJDpCh8ji9OtGJgD2QejAvifzWV0dkvwZf6U0mki71v3SETEcIvxidvh8xbOv0zK0plY/4GOAQPxKDxQ/8i8lzDleCaYArOK8q2LKAr3su5R3r2sXDtrOYUpvG4yb62zjZyMbJulL2u/QQbjpzJh63MPwD0jgiSNXXb5yKop1t+O3EuqDpsUrcLKBtZ9URFee5d1hdgrPaJ9U X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3371c5e8-e16e-4d30-144c-08d9299054d3 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2021 08:43:32.6274 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Jrm9z5NeYvGAgsk54Q64AMDhWbWvD1TQp0iQ29cVMBcAKnFwYxMH0cZlKZcnfftCY1KeYf86ZX5+qQ8grIiJuQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR04MB2977 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add devicetree binding documentation for IMX8Q Video Processing Unit IP Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- .../bindings/media/nxp,imx8q-vpu.yaml | 198 ++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml diff --git a/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml new file mode 100644 index 000000000000..058ca69c107a --- /dev/null +++ b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nxp,imx8q-vpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8Q video encode and decode accelerators + +maintainers: + - Ming Qian + - Shijie Qin + +description: |- + The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present + on NXP i.MX8Q SoCs. + +allOf: + - $ref: /schemas/simple-bus.yaml# + +properties: + $nodename: + pattern: "^vpu-bus@[0-9a-f]+$" + + compatible: + contains: + items: + - enum: + - nxp,imx8qm-vpu + - nxp,imx8qxp-vpu + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + memory-region: + description: + Phandle to a node describing reserved memory used by VPU. + (see bindings/reserved-memory/reserved-memory.txt) + + mailbox: + description: + Each vpu encoder or decoder correspond a MU, which used for communication + between driver and firmware. Implement via mailbox on driver. + (see bindings/mailbox/fsl,mu.yaml) + +patternProperties: + "^vpu_[en, de]coder@[0-9a-f]+$": + type: object + description: + Each core correspond a decoder or encoder, need to configure them + separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC + has one decoder and one encoder. + + properties: + compatible: + oneOf: + - const: nxp,imx8q-vpu-decoder + - const: nxp,imx8q-vpu-encoder + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + mbox-names: + items: + - const: tx0 + - const: tx1 + - const: rx + + mboxes: + description: + List of phandle of 2 MU channels for tx, 1 MU channel for rx. + + boot-region: + description: + Phandle to a node describing reserved memory used by firmware + loading. + + rpc-region: + description: + Phandle to a node describing reserved memory used by RPC shared + memory between firmware and driver. + + print-offset: + description: + The memory offset from RPC address, used by reserve firmware log. + + id: + description: Index of vpu core. + + required: + - compatible + - reg + - power-domains + - mbox-names + - mboxes + - boot-region + - rpc-region + - print-offset + - id + + additionalProperties: false + +required: + - compatible + - reg + - power-domains + - memory-region + +additionalProperties: true + +examples: + # Device node example for i.MX8QM platform: + - | + #include + + vpu: vpu-bus@2c000000 { + compatible = "nxp,imx8qm-vpu", "simple-bus"; + ranges = <0x2c000000 0x2c000000 0x2000000>; + reg = <0x2c000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&pd IMX_SC_R_VPU>; + memory-region = <&vpu_reserved>; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = <0 472 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = <0 473 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = <0 474 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + }; + + vpu_core0: vpu_decoder@2d080000 { + compatible = "nxp,imx8q-vpu-decoder"; + reg = <0x2d080000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0 + &mu_m0 0 1 + &mu_m0 1 0>; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + print-offset = <0x180000>; + id = <0>; + }; + + vpu_core1: vpu_encoder@2d090000 { + compatible = "nxp,imx8q-vpu-encoder"; + reg = <0x2d090000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0>; + boot-region = <&encoder1_boot>; + rpc-region = <&encoder1_rpc>; + print-offset = <0x80000>; + id = <1>; + }; + + vpu_core2: vpu_encoder@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0 + &mu2_m0 0 1 + &mu2_m0 1 0>; + boot-region = <&encoder2_boot>; + rpc-region = <&encoder2_rpc>; + print-offset = <0x80000>; + id = <2>; + }; + }; + +...