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Fri, 15 Oct 2021 08:23:39 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v11 12/13] firmware: imx: scu-pd: imx8q: add vpu mu resources Date: Fri, 15 Oct 2021 16:22:01 +0800 Message-Id: <969b83cf0d75298b53cc25b756ac289de843f9b8.1634282966.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: References: X-ClientProxiedBy: SI2PR02CA0003.apcprd02.prod.outlook.com (2603:1096:4:194::13) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SI2PR02CA0003.apcprd02.prod.outlook.com (2603:1096:4:194::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kSZZAFObdEbOM5KvhTFzOyhGNo+ThsypLPbCQEk1iJxCg72f+k1kD1b3Oez3B3cz8PWAZEeGIChaTejRoqhnihT7h3K3dLp92ftxEoKPwlxVZmVfpEBM7zVzBEbqSOQKqxakmtcNZtAvZhhCmIegXKIry8lmedy7xwe7y+GCCEc9I8EvNY0PW822FnCEgpie9x9CReBndFfEC/IfvO/RZQ8XhNKLEN9MXPhBMRTq6NQuADdSciv2gIgVY8bKatabSSJxA3Myi4BsNXVRBFqx44ZTGaTp4LWWYTqoXrZy6r1QvAKrIw7fmklsDBS5Xt0eQZC8RnDyNxQUeAxy1fNej8jkmDKgMA0IEBLxmjS5RSID+vzURKqob9EI1RpHGR8nMa1gHJDS5vndkrAtFZ9E31A32yPcxpL2h0VxsjPzGsEi5F1lqYWuRxbYcVXyrgCY4o0IBZWvrZRCR2KPQHaaAFzsRCKfPXqz/ob94Rk9/Z1RG4ajq8mVUBqWkthdDSgbjMx1pDb3fk7nHUiO/WCF58VZnJYsRywDhAucXQz9io7xHRSaq2mYnJyaKhZ0pUYvKFv6/GhrEjATb9eE6LWcWSGNrTif5oErzoHw5vTzAtRLufetIAeAJffRhSO6W3Ua6Yq42ivSsKsH1Z9tluzc4OrioxFyVPZ+gnYZ1mRJyhVB5ixR2a/PPdMiKAt01uqhd2kbIytcvzX7/EUKbVXIZTlLEWq4BU5kwWGx6SYq7HQRyGb3mbIbS0L1oVQggdio36h8ZDmkTXri4fd/ZxsMnFM97Q1r7DvJU7iGtvjZ4c8Hw043vQ+eHJ0WA7Qcmf4PLXycradAe5gVz1haHh84v3AWOpvZwAQLBbW3AaCUegcWOVAtBqyOeMKdpRbZbmyHKitwU4GGHh6qAgPV7Xl2m9O8CBW5j3TKOrnrcPFnbwV1RGm3awic+Lo94OXknzHlHpyosrfYyKneE14zxCGV2LksQwPIDZ3nsyN4F9cMqJHEdqldvtYyylCfl828QvnRC9LsjiMYFqzuoJQhovA9i9KT1cIHlWvpLwLLJ2vtiM8Z+BYHZDDnGrdQONn7HE2470b0A6mgmFlGpwgf/ftBVuUUYn6JvTKtsBwWU577oRKVThRunLx7464hWpMcMKgRFuSROdQZebHzpdKK6EWRexDSCSn8wwzfVPj5hMCS4RMJeSrnYksK216GyYeyv8s63N7q72UhrdSbvSMYgwRp/wAYEnO3T85iLJSFox++ft7DBffHRLZrAzC82NXa1qlKBLGNeT5gyUkc7JRHhlVIR24iijwKZ2Mas3rXDrx2Cjl5oJFGd0F6GXd5HcX2g5E/ X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: da5592bd-3976-43a1-c4a0-08d98fb516fb X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2021 08:23:39.0065 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: eJ1lqFqxtwd6CptZ3HfGZI5uTCNhflwESyL4jgJYJ/S+F3NZ60XhDIK504rcz7MdUOHfdvokehGEqV7JZLNzKA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0402MB3591 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org the vpu core depends on the mu resources. if they're missed, the vpu can't work. Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- drivers/firmware/imx/scu-pd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index ff6569c4a53b..af3d057e6421 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -155,6 +155,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },