From patchwork Tue Sep 11 15:51:08 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 1438761 Return-Path: X-Original-To: patchwork-linux-media@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 8871C3FC33 for ; Tue, 11 Sep 2012 15:51:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759594Ab2IKPv2 (ORCPT ); Tue, 11 Sep 2012 11:51:28 -0400 Received: from moutng.kundenserver.de ([212.227.126.171]:61766 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759562Ab2IKPv0 (ORCPT ); Tue, 11 Sep 2012 11:51:26 -0400 Received: from axis700.grange (dslb-094-220-153-146.pools.arcor-ip.net [94.220.153.146]) by mrelayeu.kundenserver.de (node=mreu1) with ESMTP (Nemesis) id 0MCuYR-1TJTLj360Z-009C0p; Tue, 11 Sep 2012 17:51:09 +0200 Received: by axis700.grange (Postfix, from userid 1000) id 504A1189B0D; Tue, 11 Sep 2012 17:51:08 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by axis700.grange (Postfix) with ESMTP id 4D436189AF7; Tue, 11 Sep 2012 17:51:08 +0200 (CEST) Date: Tue, 11 Sep 2012 17:51:08 +0200 (CEST) From: Guennadi Liakhovetski X-X-Sender: lyakh@axis700.grange To: Linux Media Mailing List cc: Stephen Warren , Sylwester Nawrocki , Laurent Pinchart , Magnus Damm , devicetree-discuss , linux-sh@vger.kernel.org, Mark Brown , Hans Verkuil , Marek Szyprowski , Arnd Bergmann , linux-arm-kernel@lists.infradead.org Subject: [PATCH] media: add V4L2 DT binding documentation Message-ID: MIME-Version: 1.0 X-Provags-ID: V02:K0:Jh20wcUhwuj+tlcoWl5c8Q8irj8h6P98Klqo8Ulpyv9 sOJhcdjehRztKYU247GbiYeBtHo7TIOq+LWeG1DYAyb4V4gqFi msdCorC8Z7CFJHtU6KLDkzskXBAoWuCwd3PPOotfVGZekMHzk0 LtPnZ+Dpl52dmp5fHiYDOGIzt2Vnx39kdPZlprud/qqgwnCGEz 9CKM8pSfFdriLQbLU5ccjZaqdgvZgISVUKf4qGhE2hb3SPC7c1 iys79P9/BSUI5JhRrRV6alitcE8CTsVAiNrFSyEgOIxjqmeVLi 8IClbc0GD2uo/BIbn21Es15vYk+yNNe68fZPOzvHr1LTN6YTZd pILgOOifkyuOlJWmNIf37iWmnWwMXvE0JafF2PiilkoqHZ45cn JwJl0FpYdL/RQ== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This patch adds a document, describing common V4L2 device tree bindings. Co-authored-by: Sylwester Nawrocki Signed-off-by: Guennadi Liakhovetski Acked-by: Stephen Warren --- Documentation/devicetree/bindings/media/v4l2.txt | 143 ++++++++++++++++++++++ 1 files changed, 143 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/v4l2.txt diff --git a/Documentation/devicetree/bindings/media/v4l2.txt b/Documentation/devicetree/bindings/media/v4l2.txt new file mode 100644 index 0000000..55da6de --- /dev/null +++ b/Documentation/devicetree/bindings/media/v4l2.txt @@ -0,0 +1,143 @@ +Video4Linux Version 2 (V4L2) + +General concept: +- video pipelines consist of external devices, e.g., camera sensors, controlled + over an I2C bus, and SoC internal IP blocks, including video DMA engines and + video data processors. +- this document describes common bindings of all video pipeline devices. +- SoC internal blocks are described by DT nodes, placed similarly to other SoC + blocks. +- external devices are places on their respective control busses, e.g., I2C +- data interfaces on all video devices are described by "port" child DT nodes +- port configuration depends on other devices, participating in the data + transfer, and is described by "link" DT nodes, specified as children of + all "port" nodes, connected to this bus. +- if a port can be configured to work with more than one other device on the + same bus, a "link" child DT node must be provided for each of them. +- if more than one port is present on a device or more than one link is + connected to a port, a common scheme, using "#address-cells," "#size-cells" + and "reg" properties is used. + +Optional link properties: +- remote: phandle to the other endpoint link DT node. +- data-shift: on parallel data busses, if data-width is used to specify the + number of data lines, data-shift can be used to specify which data lines are + used, e.g., "data-width=<10>; data-shift=<2>;" means, that lines 9:2 are used. +- hsync-active: 1 or 0 for active-high or -low HSYNC signal polarity + respectively. +- vsync-active: ditto for VSYNC. Note, that if HSYNC and VSYNC polarities are + not specified, embedded synchronisation may be required, where supported. +- pclk-sample: rising (1) or falling (0) edge to sample the pixel clock pin. +- immutable: used for SoC-internal links, if no configuration is required. +- data-lanes: array of serial, e.g., MIPI CSI-2, data hardware lane numbers in + the ascending order, beginning with logical lane 0. +- clock-lanes: hardware lane number, used for the clock lane. + +Example: + + ceu0: ceu@0xfe910000 { + compatible = "renesas,sh-mobile-ceu"; + reg = <0xfe910000 0xa0>; + interrupts = <0x880>; + + mclk: master_clock { + compatible = "renesas,ceu-clock"; + #clock-cells = <1>; + clock-frequency = <50000000>; /* max clock frequency */ + clock-output-names = "mclk"; + }; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ceu0_1: link@1 { + reg = <1>; /* local link # */ + remote = <&ov772x_1_1>; /* remote phandle */ + bus-width = <8>; /* used data lines */ + data-shift = <0>; /* lines 7:0 are used */ + + /* If [hv]sync-active are missing, embedded bt.605 sync is used */ + hsync-active = <1>; /* active high */ + vsync-active = <1>; /* active high */ + pclk-sample = <1>; /* rising */ + }; + + ceu0_0: link@0 { + reg = <0>; + remote = <&csi2_2>; + immutable; + }; + }; + }; + + i2c0: i2c@0xfff20000 { + ... + ov772x_1: camera@0x21 { + compatible = "omnivision,ov772x"; + reg = <0x21>; + vddio-supply = <®ulator1>; + vddcore-supply = <®ulator2>; + + clock-frequency = <20000000>; + clocks = <&mclk 0>; + clock-names = "xclk"; + + port { + /* With 1 link per port no need in addresses */ + ov772x_1_1: link { + bus-width = <8>; + remote = <&ceu0_1>; + hsync-active = <1>; + hsync-active = <0>; /* who came up with an inverter here?... */ + pclk-sample = <1>; + }; + }; + }; + + imx074: camera@0x1a { + compatible = "sony,imx074"; + reg = <0x1a>; + vddio-supply = <®ulator1>; + vddcore-supply = <®ulator2>; + + clock-frequency = <30000000>; /* shared clock with ov772x_1 */ + clocks = <&mclk 0>; + clock-names = "sysclk"; /* assuming this is the name in the datasheet */ + + port { + imx074_1: link { + clock-lanes = <0>; + data-lanes = <1>, <2>; + remote = <&csi2_1>; + }; + }; + }; + }; + + csi2: csi2@0xffc90000 { + compatible = "renesas,sh-mobile-csi2"; + reg = <0xffc90000 0x1000>; + interrupts = <0x17a0>; + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + compatible = "renesas,csi2c"; /* one of CSI2I and CSI2C */ + reg = <1>; /* CSI-2 PHY #1 of 2: PHY_S, PHY_M has port address 0, is unused */ + + csi2_1: link { + clock-lanes = <0>; + data-lanes = <2>, <1>; + remote = <&imx074_1>; + }; + }; + port@2 { + reg = <2>; /* port 2: link to the CEU */ + + csi2_2: link { + immutable; + remote = <&ceu0_0>; + }; + }; + };