From patchwork Wed Apr 12 19:30:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiner Kallweit X-Patchwork-Id: 9678287 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B9AD3601C3 for ; Wed, 12 Apr 2017 19:35:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A87F028615 for ; Wed, 12 Apr 2017 19:35:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9BDA928641; Wed, 12 Apr 2017 19:35:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F079828615 for ; Wed, 12 Apr 2017 19:35:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754640AbdDLTfO (ORCPT ); Wed, 12 Apr 2017 15:35:14 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:32859 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754634AbdDLTfN (ORCPT ); Wed, 12 Apr 2017 15:35:13 -0400 Received: by mail-wm0-f65.google.com with SMTP id o81so8553190wmb.0 for ; Wed, 12 Apr 2017 12:35:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:from:to:cc:references:message-id:date:user-agent :mime-version:in-reply-to:content-transfer-encoding; bh=kCxnLnVYWrjcRIGWsSsTsHtG7abrKJoFChPA5t1IK70=; b=cLbLZzwaaezCw1GCgpgky1AxJa8+taJMDFJ9dhIkwzEAZItOrz4lchSsqFB44xZ1Al Pc5Fvlf7SszmiKYqL0fETNesJY/mbQA7AgGFmxZG5IxSPNSmxcR2t6hmXCq0yd9j3Cc+ FmKWmMtX9xO/iARzWDTrbbX+C0oZqy63hxD9HDeLPdvTU3+RsaxOwyi3cfEOy9KGh3VJ UDHM2rK76l/vU0UMhunekFSvIcXixM7OpMQINp8sqy5yQfB+YrXGvHiecBa6jvM6eGFd 7PGoMjR0IDsAF02lGXmcZTbeDJL2PBg1O8CnGuxvZE3iczYRHiFY6P8L/B5W3r+CFXJi P7Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:cc:references:message-id:date :user-agent:mime-version:in-reply-to:content-transfer-encoding; bh=kCxnLnVYWrjcRIGWsSsTsHtG7abrKJoFChPA5t1IK70=; b=e0RKxqCJUNsBF2QMn5f35wqNBD9dOZ0ij3pgKqsGuUR4E66sRwGv3VzrWrulKcHpBo c6kOOiOHJn3icu7Ev8b0bRs0QiN0BDpGJVbum/IKLFLkPiwforeRL4Ph1DnvH9RYIa5s No9AggZ7hdr0EIeWRurvZvZeyyhugDFBCa8u0VIYlqpQrgJPQdoCuU9nVoNdWbWQeCvx 6TQ6azuIyxkjDCNsOGhhcKnr/4uFhZF/JqLcH2i9mhHRFFimGqscV9a53dkNtKgkzwve ps3rJj53T2j4TbJE7bhQEvMRRKDIqdwz772ck56tQiEA95s7qVea6e2PYPguoqTndOSK dVgQ== X-Gm-Message-State: AN3rC/4l43vQL2wTROoWTegUvMYP2D/MukwpCpd1uofscVY/a5UXAW4o b1ycF0QN0wV1xQ== X-Received: by 10.28.217.142 with SMTP id q136mr21800986wmg.48.1492025711845; Wed, 12 Apr 2017 12:35:11 -0700 (PDT) Received: from ?IPv6:2003:c6:ebdc:4000:f514:8038:dab0:5880? (p200300C6EBDC4000F5148038DAB05880.dip0.t-ipconnect.de. [2003:c6:ebdc:4000:f514:8038:dab0:5880]) by smtp.googlemail.com with ESMTPSA id i144sm7705869wmf.13.2017.04.12.12.35.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 12 Apr 2017 12:35:11 -0700 (PDT) Subject: [PATCH v2 2/5] media: rc: meson-ir: make use of the bitfield macros From: Heiner Kallweit To: Mauro Carvalho Chehab , Sean Young , Kevin Hilman , Neil Armstrong Cc: linux-media@vger.kernel.org, linux-amlogic@lists.infradead.org References: Message-ID: Date: Wed, 12 Apr 2017 21:30:48 +0200 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.0 MIME-Version: 1.0 In-Reply-To: Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Make use of the bitfield macros thus partially hiding the complexity of dealing with bitfields. The patch also includes a minor fix to REG0_RATE_MASK, so far it was set to bit 0..10, but according to the spec it's bit 0..11. Signed-off-by: Heiner Kallweit Reviewed-by: Neil Armstrong --- v2: - revert change in meson_ir_set_mask - add R-b --- drivers/media/rc/meson-ir.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c index a4128d7c..3864ebe3 100644 --- a/drivers/media/rc/meson-ir.c +++ b/drivers/media/rc/meson-ir.c @@ -19,6 +19,7 @@ #include #include #include +#include #include @@ -36,27 +37,24 @@ /* only available on Meson 8b and newer */ #define IR_DEC_REG2 0x20 -#define REG0_RATE_MASK (BIT(11) - 1) +#define REG0_RATE_MASK GENMASK(11, 0) #define DECODE_MODE_NEC 0x0 #define DECODE_MODE_RAW 0x2 /* Meson 6b uses REG1 to configure the mode */ #define REG1_MODE_MASK GENMASK(8, 7) -#define REG1_MODE_SHIFT 7 /* Meson 8b / GXBB use REG2 to configure the mode */ #define REG2_MODE_MASK GENMASK(3, 0) -#define REG2_MODE_SHIFT 0 -#define REG1_TIME_IV_SHIFT 16 -#define REG1_TIME_IV_MASK ((BIT(13) - 1) << REG1_TIME_IV_SHIFT) +#define REG1_TIME_IV_MASK GENMASK(28, 16) -#define REG1_IRQSEL_MASK (BIT(2) | BIT(3)) -#define REG1_IRQSEL_NEC_MODE (0 << 2) -#define REG1_IRQSEL_RISE_FALL (1 << 2) -#define REG1_IRQSEL_FALL (2 << 2) -#define REG1_IRQSEL_RISE (3 << 2) +#define REG1_IRQSEL_MASK GENMASK(3, 2) +#define REG1_IRQSEL_NEC_MODE 0 +#define REG1_IRQSEL_RISE_FALL 1 +#define REG1_IRQSEL_FALL 2 +#define REG1_IRQSEL_RISE 3 #define REG1_RESET BIT(0) #define REG1_ENABLE BIT(15) @@ -91,7 +89,7 @@ static irqreturn_t meson_ir_irq(int irqno, void *dev_id) spin_lock(&ir->lock); duration = readl(ir->reg + IR_DEC_REG1); - duration = (duration & REG1_TIME_IV_MASK) >> REG1_TIME_IV_SHIFT; + duration = FIELD_GET(REG1_TIME_IV_MASK, duration); rawir.duration = US_TO_NS(duration * MESON_TRATE); rawir.pulse = !!(readl(ir->reg + IR_DEC_STATUS) & STATUS_IR_DEC_IN); @@ -170,16 +168,16 @@ static int meson_ir_probe(struct platform_device *pdev) /* Set general operation mode (= raw/software decoding) */ if (of_device_is_compatible(node, "amlogic,meson6-ir")) meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK, - DECODE_MODE_RAW << REG1_MODE_SHIFT); + FIELD_PREP(REG1_MODE_MASK, DECODE_MODE_RAW)); else meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK, - DECODE_MODE_RAW << REG2_MODE_SHIFT); + FIELD_PREP(REG2_MODE_MASK, DECODE_MODE_RAW)); /* Set rate */ meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1); /* IRQ on rising and falling edges */ meson_ir_set_mask(ir, IR_DEC_REG1, REG1_IRQSEL_MASK, - REG1_IRQSEL_RISE_FALL); + FIELD_PREP(REG1_IRQSEL_MASK, REG1_IRQSEL_RISE_FALL)); /* Enable the decoder */ meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, REG1_ENABLE);