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Mon, 31 May 2021 02:51:54 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/5] dt-bindings: media: imx8q: add imx video codec bindings Date: Mon, 31 May 2021 10:51:09 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: X-Originating-IP: [119.31.174.70] X-ClientProxiedBy: MA1PR01CA0160.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::30) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by MA1PR01CA0160.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.20 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: +se/4jMQypB4kzZRhQap/DSl4xLrqHCX6SC01EnrBvX2pCXDRJEZQVJYW1XIDfP6Dj2+AvcK4aq4joNMf7bQALzjkCDNNtKfVSK1JG+0/g8WPArrcIsGTS+TVZdPQt/Ntotqvs8r19KQkGxY6PV8KKo0NsfnvxZtuZbYsxZxI66vMAljVeo311XYrTvf0NLA9GsIVBnCFEU7hD2HdnOeOpVWXj/Zuqdd8IMkhb/edxIonGJiUa58y+TJvpgDawwJg9ULasf+RnFz15rmonIxE650oeEGugjGZfZ2ATgKgGxs3ZkrMySr9ylZIpAjXcCQo5lSdnkwrDZ/zp2nat7lAOC7cNFocPc4PUQSkZR9Ojhd5GBQd7utAv4axoD6PVFuw6dZe2ETL4IOAhalji1BUDWcWlM/LI6pMX0zT2bD3GH5uBvwNkQ4BWYHk+Ilt8dVuGdHdrqp7gcsGo9NKrcERXwYlTguEue1mouVA79YVqFBbAiaeAwY1+QojP73gdAR+ZO2Sid6oIm+sQG7ciBKz/WMoOtk4SfPF32gizp29HtppNl5wy/GY9hRY202oMVLS1xF+Wha+GxkqlX03lrnsfhf705FY6X61wLnI9Ls5fL2FU/tRSCRvEbPXwGCqEHcdmOvKBlXZBp9Jy01nHdOw4WG7khHovR4Q/Cbt/sP30qNLR2T0XhxQc/2dE9peA8Ah/XB6cszpi//7L29BzEEyu95oLRkSVdmDFlMIOS9yI/yhEc0CQC3CpU1TKoExiIOtiLk9tTvQSGkW51Ep5JVMh21qVCi114gl5TKHiksUmHonB/XwKR58GUL0AGdXIeAZOiP+wJv1Mx0kP3KS+/ocFyzOJhsmlbU+Yf5IFnwN+rg8u/QbWAMXTXsfBn4/pFnaxGdFmHtqZ7MD+AfCR4acrX21kvZuco2txdht2b/KzCdAEx6rYETYr19Qv3VS1TtZJTJ1WS0VxHuWMYnDq4dCYT9UF3JMSkSVd5/fBOTMAGmgAFZTBabofIlxDiVuC3OUCaOzbWyfbsFt+aEyVnie3wUsjwIb2DSRydfMOIdZjJVuZG1tsb2H7bT3YcptE3yxdbOfP0h7v38Z6e8olWaitOU8Do5Zo+xyUysDwLSboDn0/J/WejGE/hu0UcXwdjtob/N8Dq17JIfMTHAXDn79UqcfBgIVLsIJP8CduXWD8mJ2aVovfdrzfKyHtqck21Aqhiw+CkIeWw+6tWQ6rJoR+UqOWaX4Vg5TZ0Ac+zp2HEIpgDzAcZhIFMHZGNU9srCbHPdT2VgTFYqh98sHiVMXdZ0ByZXn+I+1LBSwQhbwtwI4kUL2DuVFw8sQ5S4fj7X X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 38b97f81-2809-4008-1b9d-08d923df0c5f X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2021 02:51:54.4263 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: T83xKe9HOlf+VwkIEYLGuYmgV5kVVe0i1HCEHQiE2wQ7zhNVNpAwsGJcvFPimFH3tw2P1OFkWKlOegTGu50j2g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0401MB2546 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add devicetree binding documentation for IMX8Q Video Processing Unit IP Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- .../bindings/media/nxp,imx8q-vpu.yaml | 201 ++++++++++++++++++ 1 file changed, 201 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml diff --git a/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml new file mode 100644 index 000000000000..97e428dbfdbe --- /dev/null +++ b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml @@ -0,0 +1,201 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nxp,imx8q-vpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8Q video encode and decode accelerators + +maintainers: + - ming_qian + - Shijie Qin + +description: |- + The Amphion MXC video encode and decode accelerators present on NXP i.MX8Q SoCs. + +allOf: + - $ref: /schemas/simple-bus.yaml# + +properties: + compatible: + items: + - enum: + - nxp,imx8qxp-vpu + - nxp,imx8qm-vpu + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + memory-region: + description: + Phandle to a node describing reserved memory used by VPU. + (see bindings/reserved-memory/reserved-memory.txt) + + vpu_lpcg: + description: + This is vpu Low-Power Clock Gate (LPCG) module. + + mu_m0: + description: + Each vpu core correspond a MU node, which used for communication between + driver and firmware. Implement via mailbox on driver. + + vpu_core: + type: object + additionalProperties: false + description: + Each core correspond a decoder or encoder, need to configure them + separately. + + properties: + compatible: + oneOf: + - const: nxp,imx8q-vpu-decoder + - const: nxp,imx8q-vpu-encoder + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + mbox-names: + - const: tx0 + - const: tx1 + - const: rx + + mboxes: + maxItems: 3 + description: + List of phandle of 2 MU channels for tx, 1 MU channel for rx. + + boot-region: + description: + Phandle to a node describing reserved memory used by firmware + loading. + + rpc-region: + description: + Phandle to a node describing reserved memory used by RPC shared + memory between firmware and driver. + + print-offset: + description: + The memory offset from RPC address, used by reserve firmware log. + + id: + description: Index of vpu core. + + required: + - compatible + - reg + - power-domains + - mbox-names + - mboxes + - boot-region + - rpc-region + - print-offset + - id + + +required: + - compatible + - reg + - power-domains + - memory-region + - vpu_lpcg + - mu_m0 + - vpu_core + +examples: + # Device node example for i.MX8QM platform: + - | + #include + + vpu: vpu-bus@2c000000 { + compatible = "nxp,imx8qm-vpu", "simple-bus"; + ranges = <0x2c000000 0x2c000000 0x2000000>; + reg = <0x2c000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&pd IMX_SC_R_VPU>; + memory-region = <&vpu_reserved>; + + vpu_lpcg: clock-controller@2c000000 { + compatible = "fsl,imx8qxp-lpcg-vpu"; + reg = <0x2c000000 0x2000000>; + #clock-cells = <1>; + status = "disabled"; + }; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = <0 472 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = <0 473 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = <0 474 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + }; + + vpu_core0: vpu_decoder@2d080000 { + compatible = "nxp,imx8q-vpu-decoder"; + reg = <0x2d080000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0 + &mu_m0 0 1 + &mu_m0 1 0>; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + print-offset = <0x180000>; + id = <0>; + }; + + vpu_core1: vpu_encoder@2d090000 { + compatible = "nxp,imx8q-vpu-encoder"; + reg = <0x2d090000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0>; + boot-region = <&encoder1_boot>; + rpc-region = <&encoder1_rpc>; + print-offset = <0x80000>; + id = <1>; + }; + + vpu_core2: vpu_encoder@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0 + &mu2_m0 0 1 + &mu2_m0 1 0>; + boot-region = <&encoder2_boot>; + rpc-region = <&encoder2_rpc>; + id = <2>; + }; + }; + +...