@@ -785,6 +785,24 @@ static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, u8 * b
goto exit;
}
+ /* It may need some time for the CAM to settle down, or there might be a
+ race condition between the CAM, writing HC and our last check for DA.
+ This happens, if the CAM asserts DA, just after checking DA before we
+ are setting HC. In this case it might be a bug in the CAM to keep the
+ FR bit, the lower layer/HW communication requires a longer timeout or
+ the CAM needs more time internally. But this happens in reality!
+ We need to read the status from the HW again and do the same we did
+ for the previous check for DA */
+ if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0)
+ goto exit;
+ if (status & (STATUSREG_DA | STATUSREG_RE)) {
+ if (status & STATUSREG_DA)
+ dvb_ca_en50221_thread_wakeup(ca);
+
+ status = -EAGAIN;
+ goto exit;
+ }
+
/* send the amount of data */
if ((status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_SIZE_HIGH, bytes_write >> 8)) != 0)
goto exit;