| Message ID | 20221121122957.21611-1-johnson.wang@mediatek.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Introduce MediaTek frequency hopping driver | expand |
On Mon, 21 Nov 2022 20:29:53 +0800, Johnson Wang wrote: > The purpose of this serie is to enhance frequency hopping and spread spectrum > clocking feature for MT8186. > We introduce new PLL register APIs and some helpers for FHCTL hardware control. > For MT8186 PLL driver, we replace mtk_clk_register_plls() with newly added API > to support frequency hopping and SSC function for specific PLLs. > > Changes in v5: > - Add the reviewed-by tags. > - Move binding document to bindings/clock folder. > - change some coding style in clk-pllfh.c > > [...] Applied, thanks! [1/4] clk: mediatek: Export PLL operations symbols commit: 029c936ae7e14ce49d043527087abb5f4b0ea48c [2/4] dt-bindings: clock: mediatek: Add new bindings of MediaTek frequency hopping commit: cfcefe36bf939107eeba7b1114e3d82e31f92893 [3/4] clk: mediatek: Add new clock driver to handle FHCTL hardware commit: d7964de8a8ea800910fdd4e365c42a9e7d5c54aa [4/4] clk: mediatek: Change PLL register API for MT8186 commit: 633e34d0f46ed36f1de15ede00e4b31f4d7cccae Best regards,
The purpose of this serie is to enhance frequency hopping and spread spectrum clocking feature for MT8186. We introduce new PLL register APIs and some helpers for FHCTL hardware control. For MT8186 PLL driver, we replace mtk_clk_register_plls() with newly added API to support frequency hopping and SSC function for specific PLLs. Changes in v5: - Add the reviewed-by tags. - Move binding document to bindings/clock folder. - change some coding style in clk-pllfh.c Changes in v4: - Fixup iospace error in the binding. - Use GENMASK marco and remove extra line. Changes in v3: - Change binding file name. - Add some constraints for properties. - Rename "mediatek,hopping-ssc-percents" to "mediatek,hopping-ssc-percent". - Add new config symbol. Changes in v2: - Use SoC-specific compatible instead of generic one. - Use standard clocks property and vendor-specific property in dt-binding. - Remove some unused arguments and fix some coding style. Johnson Wang (4): clk: mediatek: Export PLL operations symbols dt-bindings: clock: mediatek: Add new bindings of MediaTek frequency hopping clk: mediatek: Add new clock driver to handle FHCTL hardware clk: mediatek: Change PLL register API for MT8186 .../bindings/clock/mediatek,mt8186-fhctl.yaml | 53 ++++ drivers/clk/mediatek/Kconfig | 8 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-fhctl.c | 244 ++++++++++++++++ drivers/clk/mediatek/clk-fhctl.h | 26 ++ drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 66 ++++- drivers/clk/mediatek/clk-pll.c | 84 +++--- drivers/clk/mediatek/clk-pll.h | 55 ++++ drivers/clk/mediatek/clk-pllfh.c | 275 ++++++++++++++++++ drivers/clk/mediatek/clk-pllfh.h | 82 ++++++ 10 files changed, 841 insertions(+), 53 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml create mode 100644 drivers/clk/mediatek/clk-fhctl.c create mode 100644 drivers/clk/mediatek/clk-fhctl.h create mode 100644 drivers/clk/mediatek/clk-pllfh.c create mode 100644 drivers/clk/mediatek/clk-pllfh.h