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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FQNmff7oegrYmGhtZQDxqlJN98giwvvrsHR/6nIJ6+8F3YUJyUkiGCGYvxBmpVzYfLCKDLjL6n7ZQiQcOA336OCUTJWTJBtSXWXAH3az3A/h7ZoKrp/4IA2RIlwC/eOfPuRHnHLXH13tOe/R4LBRMFr/gwavY7r3Jsq5QZV6BKh/tZR1xPu8A1GRnyfne6BvkMzSrH6TrG+5PcaalcpQQyaohDpwrgdMDl6kkT07JpAuFlg+IGYoV9SYUwdLSjsmWRpO/QP6ntvkjJYZZIKya5+KYcMsScf+qAufPY/3PLzR7uxSRICT+BshbrGUhfhNXuMwwb8EbYI+xn4aBSV5vgGqjt4dIbilz10eBsXS2iZSu4WT6zaLuvwI/4OqDMjsyl/MFRvcS9m5Pu2InYkhPbEC08ZFWAW7ZKu0sMHci9u4+kzBOq23ruwweOTaIqH30UdeSKotWoSN5yIu1yoBgrMDhfXiZdRCOXY8lY3nDWTkZ5k/TYVABI6hrndRj+9y8tbb0cGoPk3av6KtcvVFAZArvk7nxT/A3xEKpDYmWOf7mG+eRjd4vGLvsuZWvFfqPHZTe0yYt3azynJUsczFo4OaQ5LHAylZPWFnfhjcNZTkrBAZBe3VV7cBboViv3eHdzbddapaNVW+3qpIYbcoC9l2ZD0YdzH7kPoFyl0KQKgVl0iQqSV8XHh5hr6HENAQbh1v4H2XN3oa73K5344bOuiTY4NeWez2RZkcG44ngQ25r+mxTr+sEypeNlTCN0CcG/K5YwNDI5m1h/QWFSSkQ2BbT7IFfOYkuBAO35TLtTugf+5wmP+XhuJehQkWV/m7rBymm3WlaXDRBOg0GWspTKUMdyTseG4/nggpdGXTCuKfHIRKUau6241EgfGqhT9FMkKCJtVqqZiYvsD3VIjgeQi3qAa74jVs/CoNMqUdp0YQVpVJzCnN2YrxvAyWuBzJRClgG6IUC7Xx39AZtQJgJjygmx7HO1vYTvV7/o1FLWvarjOgqe9C9VXV9N+Yv529uQYEV+2wBwUkxOLdsEgOa+QuPgWPimJtGkoXQertwMpV30V7eTiHWD5Levw5KNBuY0Qk3wFTooRzWrR+Ts2JpZEQ3rrHLEPy0N4LQd6DpJMlLFKUtCtGY+LutwhEmTiztiad3LUOJlby0o3vz74JuNJ5xdbZF/3N9iz+M3R2eEBsXPbpkIjJ1VwStroulCaQvcTe9SU8n6Vy+4d+SUQmfPvFmXA1g3gukwnS2LVBxUgde2BkBhbtUCc/deFsjaoU8MkoWfA9m/j3zyAS7mmMtkzdJSbBV+rokiBSxzeDmb0Dool1Cx16lecUYUCeIuaGX3Yif98H4GESvlhMlmS+42zYK3it3GQhwzXKYVqwYrm7QliQKJmO2X3qNQrElwrvB4N0WPnAqxWFlS8u/iqekzgqva5aWpV/wjKjdJHXo0leKkuz70Q8/OMieJe86rtk8Bc5g2L1yKoY+ibFv/1Mnw70CnEl1qP0x3tqWLuw5B1NkySxFC8jJzMLYjScWWnmB6ix1dQzzs75nRYLoqczz6Hpaol0S0ccomGR2H2Dk9egzlXZRT5geQw9VbpeSvF4 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0776e807-fdf6-4860-90eb-08db4a6e51b5 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:08.2523 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: vmnF2sshWowAAokRi4Z10m6zbZaDdeicdqlEndGwSksZN1HnQbIn5+05WvDRyRxr X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230501_110334_833407_452ED5A5 X-CRM114-Status: GOOD ( 14.30 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org What msm does during omap_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Signed-off-by: Jason Gunthorpe --- drivers/iommu/msm_iommu.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 79d89bad5132b7..26ed81cfeee897 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -443,15 +443,20 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) return ret; } -static void msm_iommu_set_platform_dma(struct device *dev) +static int msm_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct msm_priv *priv = to_msm_priv(domain); + struct msm_priv *priv; unsigned long flags; struct msm_iommu_dev *iommu; struct msm_iommu_ctx_dev *master; - int ret; + int ret = 0; + + if (domain == identity_domain || !domain) + return 0; + priv = to_msm_priv(domain); free_io_pgtable_ops(priv->iop); spin_lock_irqsave(&msm_iommu_lock, flags); @@ -468,8 +473,18 @@ static void msm_iommu_set_platform_dma(struct device *dev) } fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); + return ret; } +static struct iommu_domain_ops msm_iommu_identity_ops = { + .attach_dev = msm_iommu_identity_attach, +}; + +static struct iommu_domain msm_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &msm_iommu_identity_ops, +}; + static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t pa, size_t pgsize, size_t pgcount, int prot, gfp_t gfp, size_t *mapped) @@ -675,10 +690,10 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) } static struct iommu_ops msm_iommu_ops = { + .identity_domain = &msm_iommu_identity_domain, .domain_alloc = msm_iommu_domain_alloc, .probe_device = msm_iommu_probe_device, .device_group = generic_device_group, - .set_platform_dma_ops = msm_iommu_set_platform_dma, .pgsize_bitmap = MSM_IOMMU_PGSIZES, .of_xlate = qcom_iommu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) {