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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: yVZaYS7E9MMWB3bBSpfen/6FXO8ZPXHr+8v9aqWLeha3ikMY5E/0H+qkGCEbTXi1XCqMuXiqSEnLomeB2hTJsRR8pg7gj3tc8usBLb6ywDa7VCvbud3sCBL3RX7XYluzBEuXTnhJPuiTb0sOaMoM6puMGHdTvxxfKUPopsvJ7vexudf/KsVome5k6IqZQN2hVuoZk1O575k2zH0CrSY4JA4cvV8AamaokyLtw/588LiAL3mIi7mzQq/n3TZZlJgeH2VEzmwwNG64Nqfv5QpgOg2BCZiHzOXz+Uc+HxGe9l/ZMMi1XdkScx9KaG3E8ZIIxzcbSCqs298MzyAWBT/yFnpzVd1XOvy76cCyQog1/DzdBXjd7NI0ToVafAq650Hqtl3SGxSighcY/MuAZNAiYRJim+GjSPUEWBNnDMhGWxQN0CXGQjQwVCx3YGE4Gk+TFk9C/XaTufvYoL6cb+DqzIH24t/KCrhiJpSQGSTYk56CEL31cbY8YbrdEMoJWKpakx6/mtrW5px6MUV72iLdNRHDfOM79eRGf98ZilVz03lhDVMZfxpY57ukmBOyBWveHTopXSyRvc225O9h5CInnpI5074iIDN3FjuBO8id/YW24dj1Vzb/kjWWt6fMUNQ9Rtme8/6W/nWUNvfffAJRdPi3N2YHKhldzrPXU93RBOzwtt1scEAkYuAP8tNcDNgysPk/IFP6HNWhtQqAO+GOl+Bhi3tRgwmfD+IEwFgXvJMQCcGZrO7jgry3FfJGxOkuYqYChhrUVD8VO5l33TXduTKTsF7ibAhhhf1X+x7BQMajl+lpXs3f/2jokoJRXl/DYANDs8C4afjQuNT7hRwzcG5lkha+4Zt0mqE7H9sIwocs9CnpYhbXYl8WDZtl8oPA42TxNprYCqcJjnB1os9HgQ0kFjYh4pn5a8PJAlXZYQMjD7wzY+e7Kn2JBHyu/IyNB/K1BEg591JO2aG10XAfAZSArHh6Q/LL+D6604p/IG2RUfseekBX/AxLQi1v9r9XPpYrX8jC4XVCVbEP9Z8nPzWFwM/9hd0NYuAB7F8x3imlvhjCuXOACiwdWu2SpxbrePFsMLDiyDN/Fy5Who0RrNSU3rcU/rIwaUgCwGijjCAEceEjwl6xJez/UPSLiBbSiJtDP3Fz0OyRtj67B3/hQk5j/TJZeVp/QX6UjtmG6D9Q7fY81Sk0JpleDKKCN2/gxy/SuGdDhZ/IW9vHkCKX9hindDS1nIuGFqsdca9mqSnftc57K59vQ6iP71ERnw0YMGXo8nCRJIA2phf3pInA2oesfv3fsaO1p1SMwhDI1H4NzfaEHxZz03FS8nEseuMAB7n2h27VErjv7V5XJgVYQy+9SHNv7vg03jehOnuq0SQxe0/qS5/uDDwV+arV74xxk3enGo4w0wrWCvoUkBg0FkEWFHTSP5tXps0BjezDsohYMDkzH3ht/hW+kfHzUdwMeSYWxZsVEECDwF2gXzU/H5ScDZgFkyqGf4oZcwzh9fJ5Hr9NQNKehOcCNiyqtfUTVAsSx7l9+W+sqg34KyaSTzNLb0VA2D7TSVkyEpbDkpgsIc2BXsGTfE/RUtON5qQo X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7b2d6626-160c-4eb3-f971-08db55a0a3b8 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 00:01:03.6060 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: eNedlfQJafiHl6+zyDYvNu8nxYgoDjSlLViUl7wgtFbWL9oyzfM9FuHTIymX0kae X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6634 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230515_170131_551066_57753F8B X-CRM114-Status: GOOD ( 14.51 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org What omap does during omap_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Signed-off-by: Jason Gunthorpe --- drivers/iommu/omap-iommu.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index 537e402f9bba97..34340ef15241bc 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1555,16 +1555,31 @@ static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, omap_domain->dev = NULL; } -static void omap_iommu_set_platform_dma(struct device *dev) +static int omap_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct omap_iommu_domain *omap_domain = to_omap_domain(domain); + struct omap_iommu_domain *omap_domain; + if (domain == identity_domain || !domain) + return 0; + + omap_domain = to_omap_domain(domain); spin_lock(&omap_domain->lock); _omap_iommu_detach_dev(omap_domain, dev); spin_unlock(&omap_domain->lock); + return 0; } +static struct iommu_domain_ops omap_iommu_identity_ops = { + .attach_dev = omap_iommu_identity_attach, +}; + +static struct iommu_domain omap_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &omap_iommu_identity_ops, +}; + static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) { struct omap_iommu_domain *omap_domain; @@ -1732,11 +1747,11 @@ static struct iommu_group *omap_iommu_device_group(struct device *dev) } static const struct iommu_ops omap_iommu_ops = { + .identity_domain = &omap_iommu_identity_domain, .domain_alloc = omap_iommu_domain_alloc, .probe_device = omap_iommu_probe_device, .release_device = omap_iommu_release_device, .device_group = omap_iommu_device_group, - .set_platform_dma_ops = omap_iommu_set_platform_dma, .pgsize_bitmap = OMAP_IOMMU_PGSIZES, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = omap_iommu_attach_dev,