From patchwork Thu Jun 18 02:46:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Shu X-Patchwork-Id: 6632611 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5BD449F46B for ; Thu, 18 Jun 2015 02:47:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6F675207C5 for ; Thu, 18 Jun 2015 02:47:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 27013207B9 for ; Thu, 18 Jun 2015 02:47:20 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z5PrL-0007fp-87; Thu, 18 Jun 2015 02:47:19 +0000 Received: from [210.61.82.184] (helo=mailgw02.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z5PrF-0007aT-9f for linux-mediatek@lists.infradead.org; Thu, 18 Jun 2015 02:47:16 +0000 X-Listener-Flag: 11101 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 291678827; Thu, 18 Jun 2015 10:46:46 +0800 Received: from mtkslt201.mediatek.inc (10.21.15.54) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Thu, 18 Jun 2015 10:46:45 +0800 From: Scott Shu To: Subject: [PATCH 2/6] soc: Mediatek: Add SCPSYS CPU power domain driver Date: Thu, 18 Jun 2015 10:46:23 +0800 Message-ID: <1434595587-25466-3-git-send-email-scott.shu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1434595587-25466-1-git-send-email-scott.shu@mediatek.com> References: <1434595587-25466-1-git-send-email-scott.shu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150617_194713_777796_5A197379 X-CRM114-Status: GOOD ( 12.98 ) X-Spam-Score: 1.3 (+) Cc: scott.shu@gmail.com, linux-mediatek@lists.infradead.org, jades.shih@mediatek.com, srv_wsdupstream@mediatek.com, Miles.Chen@mediatek.com, Mars.Cheng@mediatek.com, MY.Chuang@mediatek.com, Scott Shu X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds a CPU power domain driver for the Mediatek SCPSYS unit on mt6580. --- arch/arm/mach-mediatek/Makefile | 2 +- arch/arm/mach-mediatek/generic.h | 24 +++++ arch/arm/mach-mediatek/hotplug.c | 228 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 253 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-mediatek/generic.h create mode 100644 arch/arm/mach-mediatek/hotplug.c diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 2116460..b2e4ef5 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -1,4 +1,4 @@ ifeq ($(CONFIG_SMP),y) -obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o +obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o hotplug.o endif obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o diff --git a/arch/arm/mach-mediatek/generic.h b/arch/arm/mach-mediatek/generic.h new file mode 100644 index 0000000..2a0d0c8 --- /dev/null +++ b/arch/arm/mach-mediatek/generic.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2015 Mediatek Inc. + * Author: Scott Shu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __MACH_MTK_COMMON__ +#define __MACH_MTK_COMMON__ + +#include + +int spm_cpu_mtcmos_init(void); +int spm_cpu_mtcmos_on(int cpu); +int spm_cpu_mtcmos_off(int cpu, bool wfi); + +#endif diff --git a/arch/arm/mach-mediatek/hotplug.c b/arch/arm/mach-mediatek/hotplug.c new file mode 100644 index 0000000..be0305d --- /dev/null +++ b/arch/arm/mach-mediatek/hotplug.c @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2015 Mediatek Inc. + * Author: Scott Shu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* SCPSYS registers */ +#define SPM_POWERON_CONFIG_SET 0x0000 + +#define SPM_CA7_CPU0_PWR_CON 0x0200 +#define SPM_CA7_CPU1_PWR_CON 0x0218 +#define SPM_CA7_CPU2_PWR_CON 0x021c +#define SPM_CA7_CPU3_PWR_CON 0x0220 + +#define SPM_CA7_CPU0_L1_PDN 0x025c +#define SPM_CA7_CPU1_L1_PDN 0x0264 +#define SPM_CA7_CPU2_L1_PDN 0x026c +#define SPM_CA7_CPU3_L1_PDN 0x0274 + +#define SPM_PWR_STATUS 0x060c +#define SPM_PWR_STATUS_2ND 0x0610 +#define SPM_SLEEP_TIMER_STA 0x0720 + +/* + * bit definition in SPM_CA7_CPUx_PWR_CON + */ +#define SRAM_ISOINT_B BIT(6) +#define SRAM_CKISO BIT(5) +#define PWR_CLK_DIS BIT(4) +#define PWR_ON_2ND BIT(3) +#define PWR_ON BIT(2) +#define PWR_ISO BIT(1) +#define PWR_RST_B BIT(0) + +/* + * bit definition in SPM_CA7_CPUx_L1_PDN + */ +#define L1_PDN_ACK BIT(8) +#define L1_PDN BIT(0) + +void __iomem *spm_cpu_base; + +u32 spm_cpu_pwr_con[4] = { + SPM_CA7_CPU0_PWR_CON, + SPM_CA7_CPU1_PWR_CON, + SPM_CA7_CPU2_PWR_CON, + SPM_CA7_CPU3_PWR_CON, +}; + +u32 spm_cpu_l1_pdn[4] = { + SPM_CA7_CPU0_L1_PDN, + SPM_CA7_CPU1_L1_PDN, + SPM_CA7_CPU2_L1_PDN, + SPM_CA7_CPU3_L1_PDN, +}; + +#define SPM_REGWR_EN (1U << 0) +#define SPM_PROJECT_CODE 0x0B16 + +int spm_cpu_mtcmos_on(int cpu) +{ + static DEFINE_SPINLOCK(spm_cpu_lock); + unsigned long flags; + static u32 spmcpu_pwr_con, spmcpu_l1_pdn; + unsigned int temp; + + temp = (SPM_PROJECT_CODE << 16) | SPM_REGWR_EN; + writel_relaxed(temp, spm_cpu_base + SPM_POWERON_CONFIG_SET); + + spmcpu_pwr_con = spm_cpu_pwr_con[cpu]; + spmcpu_l1_pdn = spm_cpu_l1_pdn[cpu]; + + spin_lock_irqsave(&spm_cpu_lock, flags); + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp |= PWR_ON; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + udelay(1); + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp |= PWR_ON_2ND; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + while (((readl_relaxed(spm_cpu_base + SPM_PWR_STATUS) & + (1U << (13 - cpu))) != (1U << (13 - cpu))) || + ((readl_relaxed(spm_cpu_base + SPM_PWR_STATUS_2ND) & + (1U << (13 - cpu))) != (1U << (13 - cpu)))) { + ; + } + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp &= ~PWR_ISO; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + /* L1 power on */ + temp = readl_relaxed(spm_cpu_base + spmcpu_l1_pdn); + temp &= ~L1_PDN; + writel_relaxed(temp, spm_cpu_base + spmcpu_l1_pdn); + while ((readl_relaxed(spm_cpu_base + spmcpu_l1_pdn) & + L1_PDN_ACK) != 0) + ; + + udelay(1); + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp |= SRAM_ISOINT_B; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp &= ~SRAM_CKISO; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp &= ~PWR_CLK_DIS; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp |= PWR_RST_B; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + spin_unlock_irqrestore(&spm_cpu_lock, flags); + + return 0; +} + +int spm_cpu_mtcmos_off(int cpu, bool wfi) +{ + static DEFINE_SPINLOCK(spm_cpu_lock); + unsigned long flags; + static u32 spmcpu_pwr_con, spmcpu_l1_pdn; + unsigned int temp; + + temp = (SPM_PROJECT_CODE << 16) | SPM_REGWR_EN; + writel_relaxed(temp, spm_cpu_base + SPM_POWERON_CONFIG_SET); + + spmcpu_pwr_con = spm_cpu_pwr_con[cpu]; + spmcpu_l1_pdn = spm_cpu_l1_pdn[cpu]; + + if (wfi) { + while ((readl_relaxed(spm_cpu_base + SPM_SLEEP_TIMER_STA) & + (1U << (16 + cpu))) == 0) + ; + } + + spin_lock_irqsave(&spm_cpu_lock, flags); + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp |= PWR_ISO; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp |= SRAM_CKISO; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp &= ~SRAM_ISOINT_B; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + /* L1 power off */ + temp = readl_relaxed(spm_cpu_base + spmcpu_l1_pdn); + temp |= L1_PDN; + writel_relaxed(temp, spm_cpu_base + spmcpu_l1_pdn); + while ((readl_relaxed(spm_cpu_base + spmcpu_l1_pdn) + & L1_PDN_ACK) != L1_PDN_ACK) + ; + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp &= ~PWR_RST_B; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp |= PWR_CLK_DIS; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp &= ~PWR_ON; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con); + temp &= ~PWR_ON_2ND; + writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con); + + while (((readl_relaxed(spm_cpu_base + SPM_PWR_STATUS) & + (1U << (13 - cpu))) != 0) || + ((readl_relaxed(spm_cpu_base + SPM_PWR_STATUS_2ND) & + (1U << (13 - cpu))) != 0)) + ; + + spin_unlock_irqrestore(&spm_cpu_lock, flags); + + return 0; +} + +int spm_cpu_mtcmos_init(void) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "mediatek,mt6580-scpsys"); + if (!node) { + pr_err("Missing mt6580-scpsys node in the device tree\n"); + return -EINVAL; + } + + spm_cpu_base = of_iomap(node, 0); + if (!spm_cpu_base) { + pr_err("%s: Unable to map I/O memory\n", __func__); + return -EINVAL; + } + + return 0; +}