From patchwork Mon Jun 29 15:03:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: YH Huang X-Patchwork-Id: 6689451 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 40E5BC05AC for ; Mon, 29 Jun 2015 15:05:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5FD7C20425 for ; Mon, 29 Jun 2015 15:05:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 95052205B8 for ; Mon, 29 Jun 2015 15:05:26 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z9acf-0008Vl-Sd; Mon, 29 Jun 2015 15:05:25 +0000 Received: from [210.61.82.184] (helo=mailgw02.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z9ac5-00077f-F3; Mon, 29 Jun 2015 15:04:50 +0000 X-Listener-Flag: 11101 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1243385324; Mon, 29 Jun 2015 23:04:08 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Mon, 29 Jun 2015 23:04:06 +0800 From: YH Huang To: Matthias Brugger , Mark Rutland , Thierry Reding Subject: [PATCH v3 1/2] dt-bindings: pwm: add MediaTek display PWM bindings Date: Mon, 29 Jun 2015 23:03:30 +0800 Message-ID: <1435590211-38854-2-git-send-email-yh.huang@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1435590211-38854-1-git-send-email-yh.huang@mediatek.com> References: <1435590211-38854-1-git-send-email-yh.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150629_080449_732329_28A950C6 X-CRM114-Status: GOOD ( 26.18 ) X-Spam-Score: -1.1 (-) Cc: linux-pwm@vger.kernel.org, YH Huang , srv_heupstream@mediatek.com, Pawel Moll , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, Sascha Hauer , yingjoe.chen@mediatek.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Document the device-tree binding of MediatTek display PWM. The clock "main" and "mm" are used to generate PWM signals. The PWM has one channel to control the backlight brightness for display. It supports MT8173 and MT6595. Change-Id: I194ca88b4e4cd01a28b8701e07e86ea6941e5292 Signed-off-by: YH Huang --- .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt new file mode 100644 index 0000000..355b755 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt @@ -0,0 +1,24 @@ +MediaTek display PWM controller + +Required properties: + - compatible: should be "mediatek,-disp-pwm" + - "mediatek,mt8173-disp-pwm": found on mt8173 SoC + - "mediatek,mt6595-disp-pwm": found on mt6595 SoC + - reg: physical base address and length of the controller's registers + - #pwm-cells: must be 2. See pwm.txt in this directory for a description of + the cell format + - clocks: phandle and clock specifier of the PWM reference clock + - clock-names: must contain the following + - "main": clock used to generate PWM signals + - "mm": sync signals from the modules of mmsys + +Example: + pwm0: pwm@1401e000 { + compatible = "mediatek,mt8173-disp-pwm", + "mediatek,mt6595-disp-pwm"; + reg = <0 0x1401e000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys MM_DISP_PWM026M>, + <&mmsys MM_DISP_PWM0MM>; + clock-names = "main", "mm"; + };