From patchwork Mon Jul 13 09:32:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yingjoe Chen X-Patchwork-Id: 6777021 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6DA009F2E8 for ; Mon, 13 Jul 2015 09:33:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9E5D3205B9 for ; Mon, 13 Jul 2015 09:33:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B3A0220557 for ; Mon, 13 Jul 2015 09:33:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEa7Z-0001vZ-Aq; Mon, 13 Jul 2015 09:33:57 +0000 Received: from [210.61.82.184] (helo=mailgw02.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEa7J-0001If-4n; Mon, 13 Jul 2015 09:33:43 +0000 X-Listener-Flag: 11101 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1960241338; Mon, 13 Jul 2015 17:33:14 +0800 Received: from mtksdtcf02.mediatek.inc (10.21.12.142) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Mon, 13 Jul 2015 17:33:13 +0800 From: Yingjoe Chen To: Matthias Brugger , Thomas Gleixner , Stephen Boyd , Michael Turquette , James Liao Subject: [PATCH 1/5] clocksource: mediatek: do not enable GPT_CLK_EVT when setup Date: Mon, 13 Jul 2015 17:32:45 +0800 Message-ID: <1436779969-18610-2-git-send-email-yingjoe.chen@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1436779969-18610-1-git-send-email-yingjoe.chen@mediatek.com> References: <1436779969-18610-1-git-send-email-yingjoe.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150713_023341_528503_4822251A X-CRM114-Status: GOOD ( 15.95 ) X-Spam-Score: -1.1 (-) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Russell King , srv_heupstream@mediatek.com, Arnd Bergmann , Catalin Marinas , Daniel Lezcano , linux-kernel@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, Sascha Hauer , Olof Johansson , Yingjoe Chen , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Spurious mtk timer interrupt is noticed at boot and cause kernel crash. It seems if GPT is enabled, it will latch irq status even when its IRQ is disabled. When irq is enabled afterward, we see spurious interrupt. Change init flow to only enable GPT_CLK_SRC at mtk_timer_init. Signed-off-by: Yingjoe Chen Reviewed-by: Daniel Kurtz Acked-by: Matthias Brugger --- drivers/clocksource/mtk_timer.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/clocksource/mtk_timer.c b/drivers/clocksource/mtk_timer.c index 68ab423..237c20b 100644 --- a/drivers/clocksource/mtk_timer.c +++ b/drivers/clocksource/mtk_timer.c @@ -156,9 +156,11 @@ static void mtk_timer_global_reset(struct mtk_clock_event_device *evt) writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG); } -static void -mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option) +static void mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, + u8 option, bool enable) { + u32 val; + writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE, evt->gpt_base + TIMER_CTRL_REG(timer)); @@ -167,8 +169,10 @@ mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option) writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer)); - writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE, - evt->gpt_base + TIMER_CTRL_REG(timer)); + val = TIMER_CTRL_OP(option); + if (enable) + val |= TIMER_CTRL_ENABLE; + writel(val, evt->gpt_base + TIMER_CTRL_REG(timer)); } static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer) @@ -235,12 +239,12 @@ static void __init mtk_timer_init(struct device_node *node) evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); /* Configure clock source */ - mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN); + mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN, true); clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC), node->name, rate, 300, 32, clocksource_mmio_readl_up); /* Configure clock event */ - mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT); + mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT, false); clockevents_config_and_register(&evt->dev, rate, 0x3, 0xffffffff);