From patchwork Thu Jan 7 21:06:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Crispin X-Patchwork-Id: 7987191 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 646D4BEEE5 for ; Fri, 8 Jan 2016 15:17:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6E8C7201BC for ; Fri, 8 Jan 2016 15:17:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 88A5A20103 for ; Fri, 8 Jan 2016 15:17:26 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aHYn8-0006Dr-6S; Fri, 08 Jan 2016 15:17:26 +0000 Received: from arrakis.dune.hu ([78.24.191.176]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aHYn4-00069G-Gs for linux-mediatek@lists.infradead.org; Fri, 08 Jan 2016 15:17:24 +0000 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id BCAA7280490; Fri, 8 Jan 2016 16:16:22 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00, DATE_IN_PAST_12_24, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (p548C906A.dip0.t-ipconnect.de [84.140.144.106]) by arrakis.dune.hu (Postfix) with ESMTPSA; Fri, 8 Jan 2016 16:16:22 +0100 (CET) From: John Crispin To: Bjorn Helgaas Subject: [PATCH 1/2] dt-bindings: add MedieTak PCIE binding documentation Date: Thu, 7 Jan 2016 22:06:12 +0100 Message-Id: <1452200773-50794-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160108_071723_053212_405917C0 X-CRM114-Status: GOOD ( 13.56 ) X-Spam-Score: -0.9 (/) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: John Crispin --- .../devicetree/bindings/pci/mediatek-pcie.txt | 140 ++++++++++++++++++++ 1 file changed, 140 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt new file mode 100644 index 0000000..1bd20b2 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt @@ -0,0 +1,140 @@ +Mediatek PCIe controller + +Required properties: +- compatible: Should be one of: + - "mediatek,mt2701-pcie" + - "mediatek,mt7623-pcie" +- device_type: Must be "pci" +- reg: A list of physical base address and length for each set of controller + registers. A list of register ranges to use. Must contain an + entry for each entry in the reg-names property. +- reg-names: Must include the following entries: + "pcie": PCIE registers + "pcie phy0": PCIE PHY0 registers + "pcie phy1": PCIE PHY0 registers + "pcie phy2": PCIE PHY0 registers +- interrupts: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. +- interrupt-names: Must include the following entries: + "pcie0": The interrupt that is asserted for port0 + "pcie1": The interrupt that is asserted for port1 + "pcie2": The interrupt that is asserted for port2 +- bus-range: Range of bus numbers associated with this controller +- #address-cells: Address representation for root ports (must be 3) +- #size-cells: Size representation for root ports (must be 2) +- ranges: Describes the translation of addresses for root ports and standard + PCI regions. The entries must be 6 cells each. + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- #interrupt-cells: Size representation for interrupts (must be 1) +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - pcie0 + - pcie1 + - pcie2 +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following entries: + - pcie0 + - pcie1 + - pcie2 +- mediatek,hifsys: Must contain a phandle to the HIFSYS syscon range. +Root ports are defined as subnodes of the PCIe controller node. + +Required properties: +- device_type: Must be "pci" +- assigned-addresses: Address and size of the port configuration registers +- reg: PCI bus address of the root port +- #address-cells: Must be 3 +- #size-cells: Must be 2 +- ranges: Sub-ranges distributed from the PCIe controller node. An empty + property is sufficient. + +Example: + +SoC DTSI: + + hifsys: clock-controller@1a000000 { + compatible = "mediatek,mt7623-hifsys", + "mediatek,mt2701-hifsys", + "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pcie-controller@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */ + <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */ + <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */ + <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */ + reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2"; + interrupts = , + , + ; + interrupt-names = "pcie0", "pcie1", "pcie2"; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "pcie"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, + <&hifsys MT2701_HIFSYS_PCIE1_RST>, + <&hifsys MT2701_HIFSYS_PCIE2_RST>; + reset-names = "pcie0", "pice1", "pcie2"; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + mediatek,hifsys = <&hifsys>; + + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */ + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */ + + status = "disabled"; + + pcie@1,0 { + device_type = "pci"; + reg = <0x0800 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + status = "disabled"; + }; + + pcie@2,0{ + device_type = "pci"; + reg = <0x1000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + status = "disabled"; + }; + + pcie@3,0{ + device_type = "pci"; + reg = <0x1800 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + status = "disabled"; + }; + }; + +Board DTS: + + pcie-controller { + status = "okay"; + + pci@1,0 { + status = "okay"; + }; + };