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From: Philipp Zabel
To: dri-devel@lists.freedesktop.org
Subject: [PATCH v9 13/14] clk: mediatek: remove hdmitx_dig_cts from TOP
clocks
Date: Tue, 12 Jan 2016 16:15:49 +0100
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Cc: Mark Rutland ,
Michael Turquette ,
Dave Airlie ,
Jie Qiu , Cawa Cheng ,
Daniel Stone , YT Shen ,
Yingjoe Chen ,
Philipp Zabel , devicetree@vger.kernel.org,
Jitao Shi , kernel@pengutronix.de,
Pawel Moll ,
Ian Campbell ,
CK Hu , Rob Herring ,
linux-mediatek@lists.infradead.org,
Matthias Brugger ,
Paul Bolle , Stephen Boyd ,
Tomasz Figa , Daniel Vetter ,
Kumar Gala
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The hdmitx_dig_cts clock signal is not a child of tvdpll_445p5m,
but is routed out of the HDMI PHY module.
Signed-off-by: Philipp Zabel
Acked-by: Stephen Boyd
---
drivers/clk/mediatek/clk-mt8173.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 3ae0b88..e0d9994 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -61,7 +61,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = {
FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
- FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "tvdpll_445p5m", 1, 3),
FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),