From patchwork Wed Jan 20 06:35:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Liao X-Patchwork-Id: 8068791 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 81258BEEE5 for ; Wed, 20 Jan 2016 06:36:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A2BB820461 for ; Wed, 20 Jan 2016 06:36:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D0CCF20456 for ; Wed, 20 Jan 2016 06:36:53 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aLmNx-0002O3-7M; Wed, 20 Jan 2016 06:36:53 +0000 Received: from [210.61.82.184] (helo=mailgw02.hq.mediatek.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aLmNN-0002B5-JB; Wed, 20 Jan 2016 06:36:20 +0000 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw02.hq.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 265027384; Wed, 20 Jan 2016 14:35:55 +0800 Received: from mtksdtcf04.mediatek.inc (10.21.12.144) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Wed, 20 Jan 2016 14:35:54 +0800 From: James Liao To: Matthias Brugger , Mike Turquette , Stephen Boyd , John Crispin , Rob Herring Subject: [PATCH v4 6/6] reset: mediatek: Add MT2701 reset driver Date: Wed, 20 Jan 2016 14:35:47 +0800 Message-ID: <1453271747-57397-7-git-send-email-jamesjj.liao@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1453271747-57397-1-git-send-email-jamesjj.liao@mediatek.com> References: <1453271747-57397-1-git-send-email-jamesjj.liao@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160119_223617_949296_6300E2D1 X-CRM114-Status: UNSURE ( 9.40 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.1 (-) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Sascha Hauer , srv_heupstream@mediatek.com, James Liao , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Shunli Wang , Philipp Zabel , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shunli Wang In infrasys and perifsys, there are many reset control bits for kinds of modules. These bits are used as actual reset controllers to be registered into kernel's generic reset controller framework. Signed-off-by: Shunli Wang Signed-off-by: James Liao Tested-by: John Crispin --- drivers/clk/mediatek/clk-mt2701.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 82f9c1c..4e5b51f 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -665,6 +665,8 @@ static void __init mtk_infrasys_init(struct device_node *node) if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); + + mtk_register_reset_controller(node, 2, 0x30); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt2701-infracfg", mtk_infrasys_init); @@ -782,6 +784,8 @@ static void __init mtk_pericfg_init(struct device_node *node) if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); + + mtk_register_reset_controller(node, 2, 0x0); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt2701-pericfg", mtk_pericfg_init); @@ -996,6 +1000,8 @@ static void __init mtk_hifsys_init(struct device_node *node) if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); + + mtk_register_reset_controller(node, 1, 0x34); } CLK_OF_DECLARE(mtk_hifsys, "mediatek,mt2701-hifsys", mtk_hifsys_init);