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[67.253.128.196]) by smtp.gmail.com with ESMTPSA id t69sm14613418qge.18.2016.03.22.06.32.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 Mar 2016 06:32:46 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, dwmw2@infradead.org, computersforpeace@gmail.com, matthias.bgg@gmail.com, robh@kernel.org, boris.brezillon@free-electrons.com Subject: [RFCv2: PATCH 1/2] mtd: mediatek: device tree docs for MTK Smart Device Gen1 NAND Date: Tue, 22 Mar 2016 09:32:39 -0400 Message-Id: <1458653560-2679-2-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1458653560-2679-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1458653560-2679-1-git-send-email-jorge.ramirez-ortiz@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160322_063309_098074_77158F2E X-CRM114-Status: GOOD ( 11.88 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-mediatek@lists.infradead.org, xiaolei.li@mediatek.com, linux-mtd@lists.infradead.org, daniel.thompson@linaro.org, erin.lo@mediatek.com MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds documentation support for Smart Device Gen1 type of NAND controllers. Mediatek's SoC 2701 is one of the SoCs that implements this controller. Signed-off-by: Jorge Ramirez-Ortiz --- .../devicetree/bindings/mtd/mtksdg1-nand.txt | 143 +++++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt b/Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt new file mode 100644 index 0000000..be6c579 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt @@ -0,0 +1,143 @@ +MTK Smart Device SoCs NAND FLASH controller (NFC) DT binding + +This file documents the device tree bindings for the Smart Device Gen1 +NAND controllers. The functional split of the controller requires two +drivers to operate: the nand controller interface driver and the ECC +controller driver. + +The hardware description for both devices must be captured as device +tree nodes. + +1) NFC NAND Controller Interface (NFI): +======================================= + +The first part of NFC is NAND Controller Interface (NFI) HW. +Required NFI properties: +- compatible: Should be "mediatek,mtxxxx-nfc". +- reg: Base physical address and size of NFI. +- interrupts: Interrupts of NFI. +- clocks: NFI required clocks. +- clock-names: NFI clocks internal name. +- status: Disabled default. Then set "okay" by platform. +- mediatek,ecc-controller: Required ECC Engine node. +- #address-cells: NAND chip index, should be 1. +- #size-cells: Should be 0. + +Example: + + nand: nfi@1100d000 { + compatible = "mediatek,mt2701-nfc"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI>, + <&pericfg CLK_PERI_NFI_PAD>; + clock-names = "nfi_clk", "pad_clk"; + nand-on-flash-bbt; + status = "disabled"; + mediatek,ecc-controller = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + }; + +Platform related properties, should be set in {platform_name}.dts: +- children nodes: NAND chips. + +Children nodes properties: +- reg: Chip Select Signal, default 0. + Set as reg = <0>, <1> when need 2 CS. +- spare_per_sector: Spare size of each sector. +- nand-ecc-strength: Number of bits to correct per ECC step. +- nand-ecc-step-size: Number of data bytes covered by a single ECC step. + +Optional: +- vmch-supply: NAND power supply. +- pinctrl-names: Default NAND pin GPIO setting name. +- pinctrl-0: GPIO setting node. + +Example: + &pio { + nand_pins_default: nanddefault { + pins_dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up; + }; + + pins_we { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + + pins_ale { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + }; + }; + + &nand { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_default>; + chip@0 { + reg = <0>; + spare_per_sector = <56>; + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + }; + }; + +NAND chip optional subnodes: +- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt + +Example: + chip@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + preloader@0 { + label = "pl"; + read-only; + reg = <0x00000000 0x00400000>; + }; + android@0x00400000 { + label = "android"; + reg = <0x00400000 0x12c00000>; + }; + }; + }; + +2) ECC Engine: +============== + +Required BCH properties: +- compatible: Should be "mediatek,mtxxxx-ecc". +- reg: Base physical address and size of ECC. +- interrupts: Interrupts of ECC. +- clocks: ECC required clocks. +- clock-names: ECC clocks internal name. +- status: Disabled default. Then set "okay" by platform. + +Example: + + bch: ecc@1100e000 { + compatible = "mediatek,mt2701-ecc"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI_ECC>; + clock-names = "nfiecc_clk"; + status = "disabled"; + };