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Received: from [210.61.82.184] (helo=mailgw02.mediatek.com) by merlin.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1ceJvC-0004jo-3U; Thu, 16 Feb 2017 11:08:22 +0000 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 548371486; Thu, 16 Feb 2017 19:07:46 +0800 Received: from mhfsdcap03.mhfswrd (10.17.3.153) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Thu, 16 Feb 2017 19:07:44 +0800 From: Long Cheng To: Vinod Koul , Rob Herring , Mark Rutland , Matthias Brugger , Russell King , Dan Williams , Greg Kroah-Hartman , Jiri Slaby Subject: [PATCH 4/4] arm: dts: mt2701: add uart APDMA to device tree Date: Thu, 16 Feb 2017 19:07:31 +0800 Message-ID: <1487243251-964-5-git-send-email-long.cheng@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1487243251-964-1-git-send-email-long.cheng@mediatek.com> References: <1487243251-964-1-git-send-email-long.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170216_060822_371843_34D11FE3 X-CRM114-Status: GOOD ( 14.73 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Long Cheng , linux-mediatek@lists.infradead.org, linux-serial@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP 1. add uart APDMA controller device node 2. add uart 0/1/2/3 DMA function 3. uart0 is console, So disable DMA 4. enable uart2 port to test DMA function. Signed-off-by: Long Cheng --- arch/arm/boot/dts/mt2701-evb.dts | 22 ++++++++++++++++++++++ arch/arm/boot/dts/mt2701.dtsi | 29 +++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index 082ca88..2f92bf9 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -24,6 +24,28 @@ }; }; +&pio { + uart2_default_cfg: uart2default { + pins_cmd_dat { + pinmux = , + , + , + ; + bias-pull-up; + }; + }; +}; + &uart0 { + dmas = ""; + dma-names = ""; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_default_cfg>; + status = "okay"; }; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 7eab6f4..62b3ec9 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -175,6 +175,23 @@ <0 0x10216000 0 0x2000>; }; + apdma: dma-controller@11000380 { + compatible = "mediatek,mt2701-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0 0x11000380 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&pericfg CLK_PERI_AP_DMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt2701-uart", "mediatek,mt6577-uart"; @@ -182,6 +199,9 @@ interrupts = ; clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0 + &apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -192,6 +212,9 @@ interrupts = ; clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2 + &apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -202,6 +225,9 @@ interrupts = ; clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; clock-names = "baud", "bus"; + dmas = <&apdma 4 + &apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -212,6 +238,9 @@ interrupts = ; clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; clock-names = "baud", "bus"; + dmas = <&apdma 6 + &apdma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; };