From patchwork Tue Aug 8 08:13:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mars Cheng X-Patchwork-Id: 9886811 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3F97C603F9 for ; Tue, 8 Aug 2017 08:15:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 317BA287E8 for ; Tue, 8 Aug 2017 08:15:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 22EE6287D3; Tue, 8 Aug 2017 08:15:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, RCVD_IN_DNSWL_NONE, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A5593287E2 for ; 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Tue, 08 Aug 2017 08:14:14 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dezeU-0003Yf-NQ for linux-mediatek@lists.infradead.org; Tue, 08 Aug 2017 08:14:12 +0000 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 58920525; Tue, 08 Aug 2017 16:13:40 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 8 Aug 2017 16:13:39 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 8 Aug 2017 16:13:38 +0800 From: Mars Cheng To: Matthias Brugger , Rob Herring , Stephen Boyd Subject: [PATCH v1 5/5] soc: mediatek: add MT6755 scpsys support Date: Tue, 8 Aug 2017 16:13:34 +0800 Message-ID: <1502180014-7995-6-git-send-email-mars.cheng@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1502180014-7995-1-git-send-email-mars.cheng@mediatek.com> References: <1502180014-7995-1-git-send-email-mars.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170808_011411_067099_475E4E35 X-CRM114-Status: GOOD ( 16.11 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Mars Cheng , linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, wsd_upstream@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This adds scpsys support for MT6755 Signed-off-by: Mars Cheng --- drivers/soc/mediatek/mtk-scpsys.c | 116 ++++++++++++++++++++++++++++++ include/dt-bindings/power/mt6755-power.h | 26 +++++++ 2 files changed, 142 insertions(+) create mode 100644 include/dt-bindings/power/mt6755-power.h diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index ceb2cc4..a745d23 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -21,6 +21,7 @@ #include #include +#include #include #include @@ -586,6 +587,118 @@ static int __init scpsys_probe_mt2701(struct platform_device *pdev) } /* + * MT6755 power domain support + */ + +static const struct scp_domain_data scp_domain_data_mt6755[] = { + [MT6755_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = PWR_STATUS_VDEC, + .ctl_offs = 0x300, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_VDEC}, + }, + [MT6755_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = PWR_STATUS_VENC, + .ctl_offs = 0x304, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .clk_id = {CLK_MM}, + }, + [MT6755_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = 0x308, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .clk_id = {CLK_MM}, + }, + [MT6755_POWER_DOMAIN_MM] = { + .name = "mm", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = 0x30C, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_MM}, + .bus_prot_mask = BIT(1), + }, + [MT6755_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = PWR_STATUS_AUDIO, + .ctl_offs = 0x314, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .clk_id = {CLK_NONE}, + }, + [MT6755_POWER_DOMAIN_MFG_ASYNC] = { + .name = "mfg_async", + .sta_mask = PWR_STATUS_MFG_ASYNC, + .ctl_offs = 0x334, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .clk_id = {CLK_MFG}, + }, + [MT6755_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = 0x338, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(16, 16), + .clk_id = {CLK_NONE}, + .bus_prot_mask = BIT(21), + }, +}; + +#define NUM_DOMAINS_MT6755 ARRAY_SIZE(scp_domain_data_mt6755) +#define SPM_PWR_STATUS_MT6755 0x0180 +#define SPM_PWR_STATUS_2ND_MT6755 0x0184 + +static int __init scpsys_probe_mt6755(struct platform_device *pdev) +{ + struct scp *scp; + struct genpd_onecell_data *pd_data; + int ret; + struct scp_ctrl_reg scp_reg; + + scp_reg.pwr_sta_offs = SPM_PWR_STATUS_MT6755; + scp_reg.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6755; + + scp = init_scp(pdev, scp_domain_data_mt6755, NUM_DOMAINS_MT6755, + &scp_reg); + if (IS_ERR(scp)) + return PTR_ERR(scp); + + mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT6755); + + pd_data = &scp->pd_data; + + ret = pm_genpd_add_subdomain(pd_data->domains[MT6755_POWER_DOMAIN_MM], + pd_data->domains[MT6755_POWER_DOMAIN_VDEC]); + if (ret && IS_ENABLED(CONFIG_PM)) + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); + + ret = pm_genpd_add_subdomain(pd_data->domains[MT6755_POWER_DOMAIN_MM], + pd_data->domains[MT6755_POWER_DOMAIN_ISP]); + if (ret && IS_ENABLED(CONFIG_PM)) + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); + + ret = pm_genpd_add_subdomain(pd_data->domains[MT6755_POWER_DOMAIN_MM], + pd_data->domains[MT6797_POWER_DOMAIN_VENC]); + if (ret && IS_ENABLED(CONFIG_PM)) + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); + + ret = pm_genpd_add_subdomain( + pd_data->domains[MT6755_POWER_DOMAIN_MFG_ASYNC], + pd_data->domains[MT6755_POWER_DOMAIN_MFG]); + if (ret && IS_ENABLED(CONFIG_PM)) + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); + + return 0; +} + +/* * MT6797 power domain support */ @@ -832,6 +945,9 @@ static int __init scpsys_probe_mt8173(struct platform_device *pdev) .compatible = "mediatek,mt2701-scpsys", .data = scpsys_probe_mt2701, }, { + .compatible = "mediatek,mt6755-scpsys", + .data = scpsys_probe_mt6755, + }, { .compatible = "mediatek,mt6797-scpsys", .data = scpsys_probe_mt6797, }, { diff --git a/include/dt-bindings/power/mt6755-power.h b/include/dt-bindings/power/mt6755-power.h new file mode 100644 index 0000000..4f9aaf4 --- /dev/null +++ b/include/dt-bindings/power/mt6755-power.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Mars.C + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_POWER_MT6755_POWER_H +#define _DT_BINDINGS_POWER_MT6755_POWER_H + +#define MT6755_POWER_DOMAIN_VDEC 0 +#define MT6755_POWER_DOMAIN_VENC 1 +#define MT6755_POWER_DOMAIN_ISP 2 +#define MT6755_POWER_DOMAIN_MM 3 +#define MT6755_POWER_DOMAIN_AUDIO 4 +#define MT6755_POWER_DOMAIN_USB 5 +#define MT6755_POWER_DOMAIN_MFG_ASYNC 6 +#define MT6755_POWER_DOMAIN_MFG 7 + +#endif /* _DT_BINDINGS_POWER_MT6755_POWER_H */