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Thu, 19 Oct 2017 02:49:32 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1e50tk-0001fU-MR; Thu, 19 Oct 2017 02:49:30 +0000 X-UUID: 20fc0767702c435eaa07b28703dbb0c9-20171019 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1078430325; Thu, 19 Oct 2017 10:49:03 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 19 Oct 2017 10:49:02 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 19 Oct 2017 10:49:02 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd , Rob Herring Subject: [PATCH v5 9/9] arm: dts: Add power controller device node of MT2712 Date: Thu, 19 Oct 2017 10:48:50 +0800 Message-ID: <1508381330-3700-10-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508381330-3700-1-git-send-email-weiyi.lu@mediatek.com> References: <1508381330-3700-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171018_194928_906384_5054104A X-CRM114-Status: GOOD ( 10.23 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP add power controller node for MT2712 Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index d2ee3cd..fa87f92 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { compatible = "mediatek,mt2712"; @@ -147,6 +148,21 @@ #clock-cells = <1>; }; + scpsys: scpsys@10006000 { + compatible = "mediatek,mt2712-scpsys", "syscon"; + #power-domain-cells = <1>; + reg = <0 0x10006000 0 0x1000>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&topckgen CLK_TOP_VENC_SEL>, + <&topckgen CLK_TOP_JPGDEC_SEL>, + <&topckgen CLK_TOP_A1SYS_HP_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>; + clock-names = "mm", "mfg", "venc", + "jpgdec", "audio", "vdec"; + infracfg = <&infracfg>; + }; + uart5: serial@1000f000 { compatible = "mediatek,mt2712-uart", "mediatek,mt6577-uart";