Message ID | 1555654680-19721-1-git-send-email-yong.liang@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [1/2] arm64: dts: mt8183: Add reset-cells in infracfg | expand |
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 08274bf..2589e94 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/mt8183-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/reset-controller/mt8183-resets.h> / { compatible = "mediatek,mt8183"; @@ -194,6 +195,7 @@ compatible = "mediatek,mt8183-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; apmixedsys: syscon@1000c000 {