| Message ID | 1568282096-13821-3-git-send-email-jiaxin.yu@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ASoC: mt8183: fix audio playback slowly after playback during bootup | expand |
On Thu, 2019-09-12 at 17:54 +0800, Jiaxin Yu wrote: > Before regmap_reinit_cache we must reset audio reg as default value. > So we use reset controller unit(toprgu) to reset audio hw. > > Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> > --- > sound/soc/mediatek/common/mtk-base-afe.h | 1 + > sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 21 +++++++++++++++++++++ > sound/soc/mediatek/mt8183/mt8183-reg.h | 6 ++++++ > 3 files changed, 28 insertions(+) > > diff --git a/sound/soc/mediatek/common/mtk-base-afe.h b/sound/soc/mediatek/common/mtk-base-afe.h > index 60cb609a9790..bccc079ee660 100644 > --- a/sound/soc/mediatek/common/mtk-base-afe.h > +++ b/sound/soc/mediatek/common/mtk-base-afe.h > @@ -60,6 +60,7 @@ struct mtk_base_afe { > void __iomem *base_addr; > struct device *dev; > struct regmap *regmap; > + struct regmap *toprgu_regmap; > struct mutex irq_alloc_lock; /* dynamic alloc irq lock */ > > unsigned int const *reg_back_up_list; > diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c > index 4a31106d3471..0e5634b3a8e3 100644 > --- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c > +++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c > @@ -1089,6 +1089,7 @@ static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev) > struct mtk_base_afe *afe; > struct mt8183_afe_private *afe_priv; > struct device *dev; > + unsigned int reg_value; > int i, irq_id, ret; > > afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); > @@ -1126,6 +1127,26 @@ static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev) > return ret; > } > > + /* toprgu_regmap init */ > + afe->toprgu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, > + "mediatek,toprgu"); > + if (IS_ERR(afe->toprgu_regmap)) { > + dev_err(dev, "could not get toprgu_regmap from dev\n"); > + return PTR_ERR(afe->toprgu_regmap); > + } > + > + /* read TOPRGUWDT_SWSYSRST, the high 8bits must be zero */ > + regmap_read(afe->toprgu_regmap, TOPRGUWDT_SWSYSRST, ®_value); > + > + /* write TOPRGUWDT_SWSYSRST, we need set high 8bits as 0x88 first */ > + reg_value |= 0x88000000; > + > + /* reset audio domain registers */ > + reg_value |= 1 << AUDIO_RST_SFT; > + regmap_write(afe->toprgu_regmap, TOPRGUWDT_SWSYSRST, reg_value); > + reg_value &= ~(1 << AUDIO_RST_SFT); > + regmap_write(afe->toprgu_regmap, TOPRGUWDT_SWSYSRST, reg_value); This register contain reset bits for many components. If components access it directly at the same time, we might have race condition. Instead, watchdog driver should export this as reset controller so this driver can access it using reset API. Joe.C
diff --git a/sound/soc/mediatek/common/mtk-base-afe.h b/sound/soc/mediatek/common/mtk-base-afe.h index 60cb609a9790..bccc079ee660 100644 --- a/sound/soc/mediatek/common/mtk-base-afe.h +++ b/sound/soc/mediatek/common/mtk-base-afe.h @@ -60,6 +60,7 @@ struct mtk_base_afe { void __iomem *base_addr; struct device *dev; struct regmap *regmap; + struct regmap *toprgu_regmap; struct mutex irq_alloc_lock; /* dynamic alloc irq lock */ unsigned int const *reg_back_up_list; diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c index 4a31106d3471..0e5634b3a8e3 100644 --- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c +++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c @@ -1089,6 +1089,7 @@ static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev) struct mtk_base_afe *afe; struct mt8183_afe_private *afe_priv; struct device *dev; + unsigned int reg_value; int i, irq_id, ret; afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); @@ -1126,6 +1127,26 @@ static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev) return ret; } + /* toprgu_regmap init */ + afe->toprgu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, + "mediatek,toprgu"); + if (IS_ERR(afe->toprgu_regmap)) { + dev_err(dev, "could not get toprgu_regmap from dev\n"); + return PTR_ERR(afe->toprgu_regmap); + } + + /* read TOPRGUWDT_SWSYSRST, the high 8bits must be zero */ + regmap_read(afe->toprgu_regmap, TOPRGUWDT_SWSYSRST, ®_value); + + /* write TOPRGUWDT_SWSYSRST, we need set high 8bits as 0x88 first */ + reg_value |= 0x88000000; + + /* reset audio domain registers */ + reg_value |= 1 << AUDIO_RST_SFT; + regmap_write(afe->toprgu_regmap, TOPRGUWDT_SWSYSRST, reg_value); + reg_value &= ~(1 << AUDIO_RST_SFT); + regmap_write(afe->toprgu_regmap, TOPRGUWDT_SWSYSRST, reg_value); + /* enable clock for regcache get default value from hw */ afe_priv->pm_runtime_bypass_reg_ctl = true; pm_runtime_get_sync(&pdev->dev); diff --git a/sound/soc/mediatek/mt8183/mt8183-reg.h b/sound/soc/mediatek/mt8183/mt8183-reg.h index e544a09e1913..8579ac4052ff 100644 --- a/sound/soc/mediatek/mt8183/mt8183-reg.h +++ b/sound/soc/mediatek/mt8183/mt8183-reg.h @@ -413,6 +413,12 @@ #define AFE_MAX_REGISTER AFE_GENERAL2_ASRC_2CH_CON13 #define AFE_IRQ_STATUS_BITS 0x1fff +/* TOPRGUWDT_SWSYSRST */ +#define TOPRGUWDT_SWSYSRST 0x18 +#define AUDIO_RST_SFT 17 +#define AUDIO_RST_MASK 0x1 +#define AUDIO_RST_MASK_SFT (0x1 << 17) + /* AUDIO_TOP_CON3 */ #define BCK_INVERSE_SFT 3 #define BCK_INVERSE_MASK 0x1
Before regmap_reinit_cache we must reset audio reg as default value. So we use reset controller unit(toprgu) to reset audio hw. Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> --- sound/soc/mediatek/common/mtk-base-afe.h | 1 + sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 21 +++++++++++++++++++++ sound/soc/mediatek/mt8183/mt8183-reg.h | 6 ++++++ 3 files changed, 28 insertions(+)