@@ -238,7 +238,6 @@ static int mtk_pll_prepare(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 r;
- u32 div_en_mask;
r = readl(pll->pwr_addr) | CON0_PWR_ON;
writel(r, pll->pwr_addr);
@@ -251,9 +250,8 @@ static int mtk_pll_prepare(struct clk_hw *hw)
r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
writel(r, pll->base_addr + REG_CON0);
- div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;
- if (div_en_mask) {
- r = readl(pll->base_addr + REG_CON0) | div_en_mask;
+ if (pll->data->en_mask) {
+ r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
writel(r, pll->base_addr + REG_CON0);
}
@@ -274,7 +272,6 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 r;
- u32 div_en_mask;
if (pll->data->flags & HAVE_RST_BAR) {
r = readl(pll->base_addr + REG_CON0);
@@ -284,9 +281,8 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
__mtk_pll_tuner_disable(pll);
- div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;
- if (div_en_mask) {
- r = readl(pll->base_addr + REG_CON0) & ~div_en_mask;
+ if (pll->data->en_mask) {
+ r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;
writel(r, pll->base_addr + REG_CON0);
}
Because all pll data has been updated. We no longer allow en_mask to be a combination of pll_en_bit and div_en_mask. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> --- drivers/clk/mediatek/clk-pll.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-)