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Fri, 04 Dec 2020 20:26:19 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Dec 2020 20:16:16 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 5 Dec 2020 12:16:13 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 5 Dec 2020 12:16:16 +0800 From: Yongqiang Niu To: Rob Herring , Matthias Brugger , CK Hu Subject: [PATCH v1, 3/5] mailbox: mediatek: add control_by_sw private data Date: Sat, 5 Dec 2020 12:15:26 +0800 Message-ID: <1607141728-17307-4-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1607141728-17307-1-git-send-email-yongqiang.niu@mediatek.com> References: <1607141728-17307-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201204_232624_559907_A3C37AA5 X-CRM114-Status: GOOD ( 10.69 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bibby Hsieh , Jassi Brar , linux-kernel@vger.kernel.org, Dennis YC Hsieh , linux-mediatek@lists.infradead.org, Yongqiang Niu , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org add control_by_sw private data Signed-off-by: Yongqiang Niu --- drivers/mailbox/mtk-cmdq-mailbox.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 5665b6e..1c01fe0 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -36,6 +36,8 @@ #define CMDQ_THR_WAIT_TOKEN 0x30 #define CMDQ_THR_PRIORITY 0x40 +#define GCE_GCTL_VALUE 0x48 + #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 #define CMDQ_THR_DISABLED 0x0 @@ -76,11 +78,13 @@ struct cmdq { struct clk *clock; bool suspended; u8 shift_pa; + bool control_by_sw; }; struct gce_plat { u32 thread_nr; u8 shift; + bool control_by_sw; }; u8 cmdq_get_shift_pa(struct mbox_chan *chan) @@ -121,6 +125,8 @@ static void cmdq_init(struct cmdq *cmdq) int i; WARN_ON(clk_enable(cmdq->clock) < 0); + if (cmdq->control_by_sw) + writel(0x7, cmdq->base + GCE_GCTL_VALUE); writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i = 0; i <= CMDQ_MAX_EVENT; i++) writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); @@ -536,6 +542,7 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->thread_nr = plat_data->thread_nr; cmdq->shift_pa = plat_data->shift; + cmdq->control_by_sw = plat_data->control_by_sw; cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, "mtk_cmdq", cmdq);