From patchwork Mon Dec 10 07:32:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 10720773 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8BA196C5 for ; Mon, 10 Dec 2018 07:43:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6CEC829C13 for ; Mon, 10 Dec 2018 07:43:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5AC0129CB8; Mon, 10 Dec 2018 07:43:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AD3B529C13 for ; Mon, 10 Dec 2018 07:43:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eHcQjZ8I5Cl276oLUI40xqrw9gEYD1mKbrysmdYh1g8=; b=iQiHID/fpPC/ZR BemRyK8lgh4z1nfkX3Qx63L2RUV3VOrZmSOQGGVweQSeQFtBX7v4Q2kJkgPHmVZLLJIwdNiqPh5EF p/x3W8pqahxGSlVbWFRKhvCrLpQ+G3ZR88hEQS5aHyseLmwsGwGQVISR0svrItdNY2Zi+tGG5EOuy YiCQZy01E7DAk7vZPJGkqJo9EKgpD2vx9CqivzNDgU8G90Smf693/GT8c32DUbTdcimqPnQSHZCN+ +qXQxZb23qLjTkrihKG6ewf2rWTX3ou90tjkS1ST13d2oy5Yuz9BWcAI9EV94f6WDo/HvxtuUerF8 9QqmE+EM+1KrW7wcI1/A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gWGDj-0002A9-Tl; Mon, 10 Dec 2018 07:43:15 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gWG41-0003d8-Rg; Mon, 10 Dec 2018 07:33:18 +0000 X-UUID: f49045a3a7924abb96e001ffd4a9d0be-20181210 X-UUID: f49045a3a7924abb96e001ffd4a9d0be-20181210 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 979354706; Mon, 10 Dec 2018 15:32:54 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 10 Dec 2018 15:32:53 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 10 Dec 2018 15:32:53 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Stephen Boyd , Rob Herring Subject: [PATCH v3 12/12] clk: mediatek: Allow changing PLL rate when it is off Date: Mon, 10 Dec 2018 15:32:40 +0800 Message-ID: <20181210073240.32278-14-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181210073240.32278-1-weiyi.lu@mediatek.com> References: <20181210073240.32278-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 9CDB393E130637978A39B52F206B72FCFBAF4381EAF1B418F905F316458A4C152000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181209_233314_295549_D3212288 X-CRM114-Status: UNSURE ( 9.93 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: James Liao Some modules may need to change its clock rate before turn on it. So changing PLL's rate when it is off should be allowed. This patch removes PLL enabled check before set rate, so that PLLs can set new frequency even if they are off. On MT8173 for example, ARMPLL's enable bit can be controlled by other HW. That means ARMPLL may be turned on even if we (CPU / SW) set ARMPLL's enable bit as 0. In this case, SW may want and can still change ARMPLL's rate by changing its pcw and postdiv settings. But without this patch, new pcw setting will not be applied because its enable bit is 0. (am from https://patchwork.kernel.org/patch/9411983/) Signed-off-by: James Liao Acked-by: Michael Turquette Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-pll.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 81400601f107..03b20e3bca4e 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -96,13 +96,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, int postdiv) { u32 con1, val; - int pll_en; u32 tuner_en = 0; u32 tuner_en_mask; void __iomem *tuner_en_addr = NULL; - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; - /* disable tuner */ if (pll->tuner_en_addr) { tuner_en_addr = pll->tuner_en_addr; @@ -141,8 +138,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, con1 = readl(pll->base_addr + REG_CON1); - if (pll_en) - con1 |= CON1_PCW_CHG; + con1 |= CON1_PCW_CHG; writel(con1, pll->base_addr + REG_CON1); if (pll->tuner_addr) @@ -155,8 +151,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, writel(val, tuner_en_addr); } - if (pll_en) - udelay(20); + udelay(20); } /*