diff mbox series

[1/3] arm64: dts: mt8183: Add gce setting in display node

Message ID 20200214044954.16923-1-bibby.hsieh@mediatek.com (mailing list archive)
State New, archived
Headers show
Series [1/3] arm64: dts: mt8183: Add gce setting in display node | expand

Commit Message

Bibby Hsieh Feb. 14, 2020, 4:49 a.m. UTC 
In order to use GCE function, we need add some information
into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

Matthias Brugger Feb. 14, 2020, 10:06 a.m. UTC | #1 
On 14/02/2020 05:49, Bibby Hsieh wrote:
> In order to use GCE function, we need add some information
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---

For the next time please provide some context on which patches this are based
on. Bet below the '---' with a link.

For this time, on which patch/series is this based? :)

Thanks,
Matthias

>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index be4428c92f35..8b522b039a37 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -9,6 +9,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/power/mt8183-power.h>
> +#include <dt-bindings/gce/mt8183-gce.h>
>  #include "mt8183-pinfunc.h"
>  
>  / {
> @@ -664,6 +665,9 @@
>  			reg = <0 0x14000000 0 0x1000>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			#clock-cells = <1>;
> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>  		};
>  
>  		ovl0: ovl@14008000 {
> @@ -672,6 +676,7 @@
>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>  		};
>  
>  		ovl_2l0: ovl@14009000 {
> @@ -680,6 +685,7 @@
>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>  		};
>  
>  		ovl_2l1: ovl@1400a000 {
> @@ -688,6 +694,7 @@
>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>  		};
>  
>  		rdma0: rdma@1400b000 {
> @@ -697,6 +704,7 @@
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>  			mediatek,rdma_fifo_size = <5120>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>  		};
>  
>  		rdma1: rdma@1400c000 {
> @@ -706,6 +714,7 @@
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>  			mediatek,rdma_fifo_size = <2048>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>  		};
>  
>  		color0: color@1400e000 {
> @@ -715,6 +724,7 @@
>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>  		};
>  
>  		ccorr0: ccorr@1400f000 {
> @@ -723,6 +733,7 @@
>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>  		};
>  
>  		aal0: aal@14010000 {
> @@ -732,6 +743,7 @@
>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>  		};
>  
>  		gamma0: gamma@14011000 {
> @@ -741,6 +753,7 @@
>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>  		};
>  
>  		dither0: dither@14012000 {
> @@ -749,6 +762,7 @@
>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>  		};
>  
>  		mutex: mutex@14016000 {
> @@ -756,6 +770,8 @@
>  			reg = <0 0x14016000 0 0x1000>;
>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>  		};
>  
>  		smi_common: smi@14019000 {
>
Matthias Brugger May 21, 2020, 10:10 a.m. UTC | #2 
On 14/02/2020 11:06, Matthias Brugger wrote:
> 
> 
> On 14/02/2020 05:49, Bibby Hsieh wrote:
>> In order to use GCE function, we need add some information
>> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>>
>> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>> ---
> 
> For the next time please provide some context on which patches this are based
> on. Bet below the '---' with a link.
> 
> For this time, on which patch/series is this based? :)

Bibby can you please help and rebase the patch against my for-next branch [1].
I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
late, but we could try :)

Thanks!
Matthias

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next

> 
> Thanks,
> Matthias
> 
>>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> index be4428c92f35..8b522b039a37 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> @@ -9,6 +9,7 @@
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>  #include <dt-bindings/interrupt-controller/irq.h>
>>  #include <dt-bindings/power/mt8183-power.h>
>> +#include <dt-bindings/gce/mt8183-gce.h>
>>  #include "mt8183-pinfunc.h"
>>  
>>  / {
>> @@ -664,6 +665,9 @@
>>  			reg = <0 0x14000000 0 0x1000>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			#clock-cells = <1>;
>> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
>> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>>  		};
>>  
>>  		ovl0: ovl@14008000 {
>> @@ -672,6 +676,7 @@
>>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>>  		};
>>  
>>  		ovl_2l0: ovl@14009000 {
>> @@ -680,6 +685,7 @@
>>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>>  		};
>>  
>>  		ovl_2l1: ovl@1400a000 {
>> @@ -688,6 +694,7 @@
>>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>>  		};
>>  
>>  		rdma0: rdma@1400b000 {
>> @@ -697,6 +704,7 @@
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>>  			mediatek,rdma_fifo_size = <5120>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>>  		};
>>  
>>  		rdma1: rdma@1400c000 {
>> @@ -706,6 +714,7 @@
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>>  			mediatek,rdma_fifo_size = <2048>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>>  		};
>>  
>>  		color0: color@1400e000 {
>> @@ -715,6 +724,7 @@
>>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>>  		};
>>  
>>  		ccorr0: ccorr@1400f000 {
>> @@ -723,6 +733,7 @@
>>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>>  		};
>>  
>>  		aal0: aal@14010000 {
>> @@ -732,6 +743,7 @@
>>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>>  		};
>>  
>>  		gamma0: gamma@14011000 {
>> @@ -741,6 +753,7 @@
>>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>>  		};
>>  
>>  		dither0: dither@14012000 {
>> @@ -749,6 +762,7 @@
>>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>>  		};
>>  
>>  		mutex: mutex@14016000 {
>> @@ -756,6 +770,8 @@
>>  			reg = <0 0x14016000 0 0x1000>;
>>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
>> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>>  		};
>>  
>>  		smi_common: smi@14019000 {
>>
Bibby Hsieh May 21, 2020, 10:47 a.m. UTC | #3 
On Thu, 2020-05-21 at 12:10 +0200, Matthias Brugger wrote:
> On 14/02/2020 11:06, Matthias Brugger wrote:
> > 
> > 
> > On 14/02/2020 05:49, Bibby Hsieh wrote:
> >> In order to use GCE function, we need add some information
> >> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> >>
> >> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> >> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> >> ---
> > 
> > For the next time please provide some context on which patches this are based
> > on. Bet below the '---' with a link.
> > 
> > For this time, on which patch/series is this based? :)
> 
> Bibby can you please help and rebase the patch against my for-next branch [1].
> I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
> late, but we could try :)

Hi, Matthias,

NP, but this patch[1] is depends on another patch [2].
Should I rebase them together into your for-next branch?

[1] https://patchwork.kernel.org/patch/11385863/
[2] https://patchwork.kernel.org/patch/11316277/

Bibby

> 
> Thanks!
> Matthias
> 
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
> 
> > 
> > Thanks,
> > Matthias
> > 
> >>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
> >>  1 file changed, 16 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> index be4428c92f35..8b522b039a37 100644
> >> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> @@ -9,6 +9,7 @@
> >>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>  #include <dt-bindings/interrupt-controller/irq.h>
> >>  #include <dt-bindings/power/mt8183-power.h>
> >> +#include <dt-bindings/gce/mt8183-gce.h>
> >>  #include "mt8183-pinfunc.h"
> >>  
> >>  / {
> >> @@ -664,6 +665,9 @@
> >>  			reg = <0 0x14000000 0 0x1000>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			#clock-cells = <1>;
> >> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> >> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> >>  		};
> >>  
> >>  		ovl0: ovl@14008000 {
> >> @@ -672,6 +676,7 @@
> >>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
> >>  		};
> >>  
> >>  		ovl_2l0: ovl@14009000 {
> >> @@ -680,6 +685,7 @@
> >>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> >>  		};
> >>  
> >>  		ovl_2l1: ovl@1400a000 {
> >> @@ -688,6 +694,7 @@
> >>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> >>  		};
> >>  
> >>  		rdma0: rdma@1400b000 {
> >> @@ -697,6 +704,7 @@
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> >>  			mediatek,rdma_fifo_size = <5120>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> >>  		};
> >>  
> >>  		rdma1: rdma@1400c000 {
> >> @@ -706,6 +714,7 @@
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> >>  			mediatek,rdma_fifo_size = <2048>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> >>  		};
> >>  
> >>  		color0: color@1400e000 {
> >> @@ -715,6 +724,7 @@
> >>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> >>  		};
> >>  
> >>  		ccorr0: ccorr@1400f000 {
> >> @@ -723,6 +733,7 @@
> >>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> >>  		};
> >>  
> >>  		aal0: aal@14010000 {
> >> @@ -732,6 +743,7 @@
> >>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> >>  		};
> >>  
> >>  		gamma0: gamma@14011000 {
> >> @@ -741,6 +753,7 @@
> >>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> >>  		};
> >>  
> >>  		dither0: dither@14012000 {
> >> @@ -749,6 +762,7 @@
> >>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> >>  		};
> >>  
> >>  		mutex: mutex@14016000 {
> >> @@ -756,6 +770,8 @@
> >>  			reg = <0 0x14016000 0 0x1000>;
> >>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> >> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
> >>  		};
> >>  
> >>  		smi_common: smi@14019000 {
> >>
>
Matthias Brugger May 21, 2020, 12:38 p.m. UTC | #4 
On 21/05/2020 12:47, Bibby Hsieh wrote:
> On Thu, 2020-05-21 at 12:10 +0200, Matthias Brugger wrote:
>> On 14/02/2020 11:06, Matthias Brugger wrote:
>>>
>>>
>>> On 14/02/2020 05:49, Bibby Hsieh wrote:
>>>> In order to use GCE function, we need add some information
>>>> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>>>>
>>>> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
>>>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>>>> ---
>>>
>>> For the next time please provide some context on which patches this are based
>>> on. Bet below the '---' with a link.
>>>
>>> For this time, on which patch/series is this based? :)
>>
>> Bibby can you please help and rebase the patch against my for-next branch [1].
>> I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
>> late, but we could try :)
> 
> Hi, Matthias,
> 
> NP, but this patch[1] is depends on another patch [2].
> Should I rebase them together into your for-next branch?
> 

I see and [2] one depends on the scpsys driver.
Then maybe better wait until we have the scpsys driver accepted.

Regards,
Matthias


> [1] https://patchwork.kernel.org/patch/11385863/
> [2] https://patchwork.kernel.org/patch/11316277/
> 
> Bibby
> 
>>
>> Thanks!
>> Matthias
>>
>> [1]
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
>>
>>>
>>> Thanks,
>>> Matthias
>>>
>>>>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>>>>  1 file changed, 16 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> index be4428c92f35..8b522b039a37 100644
>>>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> @@ -9,6 +9,7 @@
>>>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>  #include <dt-bindings/interrupt-controller/irq.h>
>>>>  #include <dt-bindings/power/mt8183-power.h>
>>>> +#include <dt-bindings/gce/mt8183-gce.h>
>>>>  #include "mt8183-pinfunc.h"
>>>>  
>>>>  / {
>>>> @@ -664,6 +665,9 @@
>>>>  			reg = <0 0x14000000 0 0x1000>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			#clock-cells = <1>;
>>>> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
>>>> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl0: ovl@14008000 {
>>>> @@ -672,6 +676,7 @@
>>>>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl_2l0: ovl@14009000 {
>>>> @@ -680,6 +685,7 @@
>>>>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl_2l1: ovl@1400a000 {
>>>> @@ -688,6 +694,7 @@
>>>>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>>>>  		};
>>>>  
>>>>  		rdma0: rdma@1400b000 {
>>>> @@ -697,6 +704,7 @@
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>>>>  			mediatek,rdma_fifo_size = <5120>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>>>>  		};
>>>>  
>>>>  		rdma1: rdma@1400c000 {
>>>> @@ -706,6 +714,7 @@
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>>>>  			mediatek,rdma_fifo_size = <2048>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>>>>  		};
>>>>  
>>>>  		color0: color@1400e000 {
>>>> @@ -715,6 +724,7 @@
>>>>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ccorr0: ccorr@1400f000 {
>>>> @@ -723,6 +733,7 @@
>>>>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>>>>  		};
>>>>  
>>>>  		aal0: aal@14010000 {
>>>> @@ -732,6 +743,7 @@
>>>>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>>>>  		};
>>>>  
>>>>  		gamma0: gamma@14011000 {
>>>> @@ -741,6 +753,7 @@
>>>>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>>>>  		};
>>>>  
>>>>  		dither0: dither@14012000 {
>>>> @@ -749,6 +762,7 @@
>>>>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>>>>  		};
>>>>  
>>>>  		mutex: mutex@14016000 {
>>>> @@ -756,6 +770,8 @@
>>>>  			reg = <0 0x14016000 0 0x1000>;
>>>>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
>>>> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>>>>  		};
>>>>  
>>>>  		smi_common: smi@14019000 {
>>>>
>>
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index be4428c92f35..8b522b039a37 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@ 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/power/mt8183-power.h>
+#include <dt-bindings/gce/mt8183-gce.h>
 #include "mt8183-pinfunc.h"
 
 / {
@@ -664,6 +665,9 @@ 
 			reg = <0 0x14000000 0 0x1000>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			#clock-cells = <1>;
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 		};
 
 		ovl0: ovl@14008000 {
@@ -672,6 +676,7 @@ 
 			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
 		};
 
 		ovl_2l0: ovl@14009000 {
@@ -680,6 +685,7 @@ 
 			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
 		};
 
 		ovl_2l1: ovl@1400a000 {
@@ -688,6 +694,7 @@ 
 			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
 		};
 
 		rdma0: rdma@1400b000 {
@@ -697,6 +704,7 @@ 
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
 			mediatek,rdma_fifo_size = <5120>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
 		};
 
 		rdma1: rdma@1400c000 {
@@ -706,6 +714,7 @@ 
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
 			mediatek,rdma_fifo_size = <2048>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
 		};
 
 		color0: color@1400e000 {
@@ -715,6 +724,7 @@ 
 			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
 		};
 
 		ccorr0: ccorr@1400f000 {
@@ -723,6 +733,7 @@ 
 			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
 		};
 
 		aal0: aal@14010000 {
@@ -732,6 +743,7 @@ 
 			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
 		};
 
 		gamma0: gamma@14011000 {
@@ -741,6 +753,7 @@ 
 			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
 		};
 
 		dither0: dither@14012000 {
@@ -749,6 +762,7 @@ 
 			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
 		};
 
 		mutex: mutex@14016000 {
@@ -756,6 +770,8 @@ 
 			reg = <0 0x14016000 0 0x1000>;
 			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
+					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
 		};
 
 		smi_common: smi@14019000 {