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[93.23.19.208]) by smtp.gmail.com with ESMTPSA id p18sm4490311wrx.47.2020.09.06.10.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2020 10:23:46 -0700 (PDT) From: Fabien Parent To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH 1/2] dt-bindings: mediatek: add MT8167 power dt-bindings Date: Sun, 6 Sep 2020 19:23:36 +0200 Message-Id: <20200906172337.1052933-1-fparent@baylibre.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200906_132348_490504_98D9E1DB X-CRM114-Status: GOOD ( 14.37 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:343 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ulf.hansson@linaro.org, krzk@kernel.org, Fabien Parent , robh+dt@kernel.org, mars.cheng@mediatek.com, macpaul.lin@mediatek.com, matthias.bgg@gmail.com, owen.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Add the SCPSYS binding documentation for MediaTek MT8167 SoCs. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/mediatek/scpsys.txt | 3 +++ include/dt-bindings/power/mt8167-power.h | 14 ++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 include/dt-bindings/power/mt8167-power.h diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index 2bc367793aec..08cb8438a35d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -10,6 +10,7 @@ domain control. The driver implements the Generic PM domain bindings described in power/power-domain.yaml. It provides the power domains defined in - include/dt-bindings/power/mt8173-power.h +- include/dt-bindings/power/mt8167-power.h - include/dt-bindings/power/mt6797-power.h - include/dt-bindings/power/mt6765-power.h - include/dt-bindings/power/mt2701-power.h @@ -26,6 +27,7 @@ Required properties: - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC - "mediatek,mt7623a-scpsys": For MT7623A SoC - "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC + - "mediatek,mt8167-scpsys" - "mediatek,mt8173-scpsys" - #power-domain-cells: Must be 1 - reg: Address range of the SCPSYS unit @@ -42,6 +44,7 @@ Required properties: Required clocks for MT6797: "mm", "mfg", "vdec" Required clocks for MT7622 or MT7629: "hif_sel" Required clocks for MT7623A: "ethif" + Required clocks for MT8167: "mm", "mfg", "vdec", "axi_mfg" Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt" Optional properties: diff --git a/include/dt-bindings/power/mt8167-power.h b/include/dt-bindings/power/mt8167-power.h new file mode 100644 index 000000000000..8e7bcb4834dc --- /dev/null +++ b/include/dt-bindings/power/mt8167-power.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_POWER_MT8167_POWER_H +#define _DT_BINDINGS_POWER_MT8167_POWER_H + +#define MT8167_POWER_DOMAIN_MM 0 +#define MT8167_POWER_DOMAIN_DISP 0 +#define MT8167_POWER_DOMAIN_VDEC 1 +#define MT8167_POWER_DOMAIN_ISP 2 +#define MT8167_POWER_DOMAIN_CONN 3 +#define MT8167_POWER_DOMAIN_MFG_ASYNC 4 +#define MT8167_POWER_DOMAIN_MFG_2D 5 +#define MT8167_POWER_DOMAIN_MFG 6 + +#endif /* _DT_BINDINGS_POWER_MT8167_POWER_H */