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Fri, 23 Oct 2020 01:14:58 -0800 Received: from mtkmbs08n2.mediatek.inc (172.21.101.56) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 02:14:56 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 17:14:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Oct 2020 17:14:54 +0800 From: Miles Chen To: Catalin Marinas , Russell King , Minchan Kim Subject: [PATCH v2 2/4] arm: mm: reordering memory type table Date: Fri, 23 Oct 2020 17:14:35 +0800 Message-ID: <20201023091437.8225-3-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201023091437.8225-1-miles.chen@mediatek.com> References: <20201023091437.8225-1-miles.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 39A6E743CB437B5F42C75816813A91AAC33538F9F78B64AC671EE6541AB26FFA2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_052731_342641_50C90F73 X-CRM114-Status: GOOD ( 17.60 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Steve Capper , wsd_upstream@mediatek.com, Will Deacon , linux-kernel@vger.kernel.org, Miles Chen , Simon Horman , linux-mediatek@lists.infradead.org, Suren Baghdasaryan , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: Minchan Kim To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that. It seems we don't need 4 bits for the memory type with ARMv6+. If it's true, let's reorder bits to make bit 5 free. We will use the bit for L_PTE_SPECIAL in next patch. A note from Catalin in [1]: " > Anyway, on ARMv7 or ARMv6+LPAE, the non-shared device gets mapped to > shared device in hardware. Looking through the arm32 code, it seems that > MT_DEVICE_NONSHARED is used by arch/arm/mach-shmobile/setup-r8a7779.c > and IIUC that's a v7 platform (R-Car H1, Cortex-A9). I think the above > should be defined to L_PTE_MT_DEV_SHARED, unless I miss any place where > DEV_NONSHARED is relevant on ARMv6 (adding Simon to confirm on shmbile). " [1] https://lore.kernel.org/patchwork/patch/986574/ Cc: Russell King Cc: Catalin Marinas Cc: Will Deacon Cc: Steve Capper Cc: Simon Horman Cc: Minchan Kim Cc: Suren Baghdasaryan Signed-off-by: Minchan Kim Signed-off-by: Miles Chen --- arch/arm/include/asm/pgtable-2level.h | 21 +++++++++++++++++---- arch/arm/mm/proc-macros.S | 4 ++-- 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index 27a8635abea0..cdcd55cca37d 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -161,14 +161,27 @@ #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */ #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ +#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ +#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */ #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ -#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ -#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ +#if defined(CONFIG_CPU_V7) || defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) +/* + * On ARMv7 or ARMv7+LPAE, the non-shared and shared device types get + * mapped to the same TEX remapping index. On classic ARMv7, the + * shareability is controlled by the PRRR[17:16] field, indexed by + * L_PTE_SHARED. On ARMv7+LPAE the device mapping is always shareable. + */ +#define L_PTE_MT_DEV_NONSHARED L_PTE_MT_DEV_SHARED +#define L_PTE_MT_DEV_WC L_PTE_MT_BUFFERABLE +#define L_PTE_MT_DEV_CACHED L_PTE_MT_WRITEBACK +#define L_PTE_MT_MASK (_AT(pteval_t, 0x07) << 2) +#else #define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ -#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x0f) << 2) /* 1111 */ -#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) +#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ +#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) +#endif #ifndef __ASSEMBLY__ diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index e2c743aa2eb2..dde1d6374250 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -137,7 +137,7 @@ .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long 0x00 @ unused + .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused @@ -147,7 +147,7 @@ .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED .long 0x00 @ unused .long 0x00 @ unused - .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS + .long 0x00 @ unused .endm .macro armv6_set_pte_ext pfx