| Message ID | 20210129073436.2429834-7-hsinyi@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/mediatek: add support for mediatek SOC MT8192 | expand |
Hi, Hsin-Yi: On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > matrix bits of mt8183 is 12 > matrix bits of mt8192 is 13 > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 22 +++++++++++++++++++--- > 1 file changed, 19 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 0c68090eb1e92..1c7163a12f3b1 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -31,8 +31,10 @@ > #define DISP_CCORR_COEF_3 0x008C > #define DISP_CCORR_COEF_4 0x0090 > > +#define CCORR_MATRIX_BITS 12 > + > struct mtk_disp_ccorr_data { > - u32 reserved; > + u32 matrix_bits; > }; > > /** > @@ -116,6 +118,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > uint16_t coeffs[9] = { 0 }; > int i; > struct cmdq_pkt *cmdq_pkt = NULL; > + u32 matrix_bits; > > if (!blob) > return; > @@ -123,8 +126,16 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > ctm = (struct drm_color_ctm *)blob->data; > input = ctm->matrix; > > - for (i = 0; i < ARRAY_SIZE(coeffs); i++) > + if (ccorr->data) > + matrix_bits = ccorr->data->matrix_bits; > + else > + matrix_bits = CCORR_MATRIX_BITS; > + > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) { > coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + if (matrix_bits > CCORR_MATRIX_BITS) > + coeffs[i] <<= (matrix_bits - CCORR_MATRIX_BITS); I think format of MT8192 ccorr coeffs is s1.11, after mtk_ctm_s31_32_to_s1_10(), you lose one bit precision. So modify mtk_ctm_s31_32_to_s1_10() to get maximum precision. Regards, CK > + } > > mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > @@ -205,8 +216,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) > return 0; > } > > +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > + .matrix_bits = CCORR_MATRIX_BITS, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > - { .compatible = "mediatek,mt8183-disp-ccorr"}, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = &mt8183_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
On Fri, 2021-01-29 at 16:40 +0800, CK Hu wrote: > Hi, Hsin-Yi: > > On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote: > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > > matrix bits of mt8183 is 12 > > matrix bits of mt8192 is 13 > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 22 +++++++++++++++++++--- > > 1 file changed, 19 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > > index 0c68090eb1e92..1c7163a12f3b1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > > @@ -31,8 +31,10 @@ > > #define DISP_CCORR_COEF_3 0x008C > > #define DISP_CCORR_COEF_4 0x0090 > > > > +#define CCORR_MATRIX_BITS 12 > > + > > struct mtk_disp_ccorr_data { > > - u32 reserved; > > + u32 matrix_bits; > > }; > > > > /** > > @@ -116,6 +118,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > > uint16_t coeffs[9] = { 0 }; > > int i; > > struct cmdq_pkt *cmdq_pkt = NULL; > > + u32 matrix_bits; > > > > if (!blob) > > return; > > @@ -123,8 +126,16 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > > ctm = (struct drm_color_ctm *)blob->data; > > input = ctm->matrix; > > > > - for (i = 0; i < ARRAY_SIZE(coeffs); i++) > > + if (ccorr->data) > > + matrix_bits = ccorr->data->matrix_bits; > > + else > > + matrix_bits = CCORR_MATRIX_BITS; > > + > > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) { > > coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > > + if (matrix_bits > CCORR_MATRIX_BITS) > > + coeffs[i] <<= (matrix_bits - CCORR_MATRIX_BITS); > > I think format of MT8192 ccorr coeffs is s1.11, after > mtk_ctm_s31_32_to_s1_10(), you lose one bit precision. So modify > mtk_ctm_s31_32_to_s1_10() to get maximum precision. > > Regards, > CK mt8183 s2.10, default value 1024 mt8192 s2.11, default value 2048 > > > + } > > > > mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > > &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > > @@ -205,8 +216,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) > > return 0; > > } > > > > +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > > + .matrix_bits = CCORR_MATRIX_BITS, > > +}; > > + > > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > > - { .compatible = "mediatek,mt8183-disp-ccorr"}, > > + { .compatible = "mediatek,mt8183-disp-ccorr", > > + .data = &mt8183_ccorr_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > >
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 0c68090eb1e92..1c7163a12f3b1 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -31,8 +31,10 @@ #define DISP_CCORR_COEF_3 0x008C #define DISP_CCORR_COEF_4 0x0090 +#define CCORR_MATRIX_BITS 12 + struct mtk_disp_ccorr_data { - u32 reserved; + u32 matrix_bits; }; /** @@ -116,6 +118,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) uint16_t coeffs[9] = { 0 }; int i; struct cmdq_pkt *cmdq_pkt = NULL; + u32 matrix_bits; if (!blob) return; @@ -123,8 +126,16 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) ctm = (struct drm_color_ctm *)blob->data; input = ctm->matrix; - for (i = 0; i < ARRAY_SIZE(coeffs); i++) + if (ccorr->data) + matrix_bits = ccorr->data->matrix_bits; + else + matrix_bits = CCORR_MATRIX_BITS; + + for (i = 0; i < ARRAY_SIZE(coeffs); i++) { coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + if (matrix_bits > CCORR_MATRIX_BITS) + coeffs[i] <<= (matrix_bits - CCORR_MATRIX_BITS); + } mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); @@ -205,8 +216,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) return 0; } +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { + .matrix_bits = CCORR_MATRIX_BITS, +}; + static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { - { .compatible = "mediatek,mt8183-disp-ccorr"}, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = &mt8183_ccorr_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);