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[86.14.42.152]) by smtp.googlemail.com with ESMTPSA id r25sm27123540wrr.64.2021.01.31.21.45.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 21:45:45 -0800 (PST) From: Bilal Wasim X-Google-Original-From: Bilal Wasim To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, matthias.bgg@gmail.com, enric.balletbo@collabora.com, hsinyi@chromium.org, weiyi.lu@mediatek.com Subject: [PATCH 2/2] soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD Date: Mon, 1 Feb 2021 10:45:42 +0500 Message-Id: <20210201054542.1470695-3-Bilal.Wasim@imgtec.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201054542.1470695-1-Bilal.Wasim@imgtec.com> References: <20210201054542.1470695-1-Bilal.Wasim@imgtec.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_004548_646723_D2762AE0 X-CRM114-Status: GOOD ( 11.33 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The mfg_async power domain in mt8173 is used to power up imgtec gpu. This domain requires the da9211 regulator to be enabled before the power domain can be enabled successfully. Signed-off-by: Bilal Wasim Reviewed-by: Hsin-Yi Wang Reported-by: kernel test robot --- drivers/soc/mediatek/mt8173-pm-domains.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h index 3e8ee5dabb43..065b8195e7d6 100644 --- a/drivers/soc/mediatek/mt8173-pm-domains.h +++ b/drivers/soc/mediatek/mt8173-pm-domains.h @@ -63,6 +63,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .ctl_offs = SPM_MFG_ASYNC_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = 0, + .caps = MTK_SCPD_DOMAIN_SUPPLY, }, [MT8173_POWER_DOMAIN_MFG_2D] = { .sta_mask = PWR_STATUS_MFG_2D,