From patchwork Thu Aug 19 02:23:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 12445857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD3BFC432BE for ; Thu, 19 Aug 2021 02:26:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B6B360551 for ; Thu, 19 Aug 2021 02:26:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9B6B360551 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=v/oyy72d+wvgJRDO1/bRKNvyZoiF+3uz9ag7JFNsGic=; b=1LV+2oE+CjlbVy jVve+BKTMBQTVMP7bV7iM41ItArkhdsX9TXEE9sk/UktrK3cwYLiHpPJmcDtc/CogpPDvg426zZl4 Hp0XksGqo9KXedHe3MA78+TqmQ2zi8N4GJ2fettYGiRyDP73SQANaQJ1MQiqa2A+ZZFbr/kIQNVE6 YsNHInXBNfw+ZSAGcaOaeLNxUPahlv1m70wCO0dYt7jzilFJT3wRLcwmyiGPwc+C0EhZ1KOpAPrBo +VDQJ6/Vx4E55Z4pHkt1Zp2ahC08FNcuh0alyReVtLZrxuY9oxAD0SUOQ+iSk02/hGRZ9Li9111kq ZWxJqW3GoQwk3npqrzzQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mGXkj-0070iq-N0; Thu, 19 Aug 2021 02:25:57 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mGXik-006zrI-Bn; Thu, 19 Aug 2021 02:23:58 +0000 X-UUID: b61f5a458845407ead152830f6b6b643-20210818 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zHfJNb394C+brLhvSOxt9N6/QhWbqwCvs4qwJwV5v40=; b=rtCExaq87p6oIaQtLFwJeSd5fhmE5E7bi0/PDkjbvuCxHbjSRJdX3FfvdA3+CvXAzAG0L1gdK5Mq2Pv2pDAfmMOY2zLo23YU7y5tDHzXRHDyeAPGyX5qYTAeczc/F73sTglJonL6aYji798wUxbq9JersyXVSDWYT9vuQVqxk50=; X-UUID: b61f5a458845407ead152830f6b6b643-20210818 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 106219137; Wed, 18 Aug 2021 19:23:47 -0700 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 18 Aug 2021 19:23:47 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 Aug 2021 10:23:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 Aug 2021 10:23:45 +0800 From: jason-jh.lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , CC: Philipp Zabel , Enric Balletbo i Serra , David Airlie , "Daniel Vetter" , Fabien Parent , , "jason-jh . lin" , Yongqiang Niu , Jitao shi , , , , , , , Subject: [PATCH v8 04/13] dt-bindings: mediatek: display: add mt8195 SoC binding Date: Thu, 19 Aug 2021 10:23:18 +0800 Message-ID: <20210819022327.13040-5-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210819022327.13040-1-jason-jh.lin@mediatek.com> References: <20210819022327.13040-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210818_192354_458472_1774FC84 X-CRM114-Status: GOOD ( 13.59 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org 1. Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE, MUTEX, OVL and RDMA yaml schema. 2. Add MERGE additional property description for mt8195 - async clock - fifo setting enable - reset controller Signed-off-by: jason-jh.lin --- .../display/mediatek/mediatek,aal.yaml | 1 + .../display/mediatek/mediatek,ccorr.yaml | 5 +++ .../display/mediatek/mediatek,color.yaml | 1 + .../display/mediatek/mediatek,dither.yaml | 5 +++ .../display/mediatek/mediatek,gamma.yaml | 5 +++ .../display/mediatek/mediatek,merge.yaml | 40 +++++++++++++++++++ .../display/mediatek/mediatek,mutex.yaml | 2 + .../display/mediatek/mediatek,ovl.yaml | 5 +++ .../display/mediatek/mediatek,rdma.yaml | 2 + 9 files changed, 66 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 7be772d77e36..e1820238db43 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -25,6 +25,7 @@ properties: - enum: - mediatek,mt2712-disp-aal - mediatek,mt8183-disp-aal + - mediatek,mt8195-disp-aal - enum: - mediatek,mt8173-disp-aal diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index 5a1c27d6b3e2..4c556a2bc64a 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -21,6 +21,11 @@ properties: oneOf: - items: - const: mediatek,mt8183-disp-ccorr + - items: + - enum: + - mediatek,mt8195-disp-ccorr + - enum: + - mediatek,mt8183-disp-ccorr reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index 9a3edf6f0b8e..a13096196a0c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -35,6 +35,7 @@ properties: - items: - enum: - mediatek,mt8183-disp-color + - mediatek,mt8195-disp-color - enum: - mediatek,mt8173-disp-color reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index 20419f876410..e89fe7393291 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -22,6 +22,11 @@ properties: oneOf: - items: - const: mediatek,mt8183-disp-dither + - items: + - enum: + - mediatek,mt8195-disp-dither + - enum: + - mediatek,mt8183-disp-dither reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index e2a1fc218e4f..dc78d6d05dee 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -23,6 +23,11 @@ properties: - const: mediatek,mt8173-disp-gamma - items: - const: mediatek,mt8183-disp-gamma + - items: + - enum: + - mediatek,mt8195-disp-gamma + - enum: + - mediatek,mt8183-disp-gamma reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index 4cdce11d7fcd..1a27b037086b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -21,6 +21,8 @@ properties: oneOf: - items: - const: mediatek,mt8173-disp-merge + - items: + - const: mediatek,mt8195-disp-merge reg: maxItems: 1 @@ -36,6 +38,31 @@ properties: clocks: items: - description: MERGE Clock + - description: MERGE Async Clock + Controlling the synchronous process between MERGE and other display function + blocks cross clock domain. + + mediatek,merge-fifo-en: + description: + The setting of merge fifo is mainly provided for the display latency buffer. + to ensure that the back-end panel display data will not be underrun, + a little more data is needed in the fifo. According to the merge fifo settings, + when the water level is detected to be insufficient, it will trigger RDMA sending + ultra and preulra command to SMI to speed up the data rate. + type: boolean + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + + resets: + description: reset controller + See Documentation/devicetree/bindings/reset/reset.txt for details. required: - compatible @@ -55,3 +82,16 @@ examples: clocks = <&mmsys CLK_MM_DISP_MERGE>; }; + merge5: disp_vpp_merge5@1c110000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c110000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; + }; + diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml index aaba6bbfb4da..0dced7a53329 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml @@ -30,6 +30,8 @@ properties: - const: mediatek,mt8173-disp-mutex - items: - const: mediatek,mt8183-disp-mutex + - items: + - const: mediatek,mt8195-disp-mutex reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index 833b0ca09b21..1973eee4244f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -31,6 +31,11 @@ properties: - mediatek,mt2712-disp-ovl - enum: - mediatek,mt2701-disp-ovl + - items: + - enum: + - mediatek,mt8195-disp-ovl + - enum: + - mediatek,mt8183-disp-ovl reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml index ce3bcca30609..847bc55252ca 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -27,6 +27,8 @@ properties: - const: mediatek,mt8173-disp-rdma - items: - const: mediatek,mt8183-disp-rdma + - items: + - const: mediatek,mt8195-disp-rdma - items: - enum: - mediatek,mt7623-disp-rdma