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[2a02:8440:6240:2cf3:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id h7sm1751938wrx.14.2021.09.29.02.46.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Sep 2021 02:46:54 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , CK Hu , Jitao shi Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/4] dt-bindings: display: mediatek: add MT8195 hdmi bindings Date: Wed, 29 Sep 2021 11:44:23 +0200 Message-Id: <20210929094425.745-3-granquet@baylibre.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210929094425.745-1-granquet@baylibre.com> References: <20210929094425.745-1-granquet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210929_024656_364029_14BC88C5 X-CRM114-Status: GOOD ( 14.89 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add Mediatek HDMI and HDMI-DDC bindings for MT8195 SoC. Signed-off-by: Guillaume Ranquet --- .../mediatek/mediatek,mt8195-hdmi-ddc.yaml | 45 +++++++++ .../mediatek/mediatek,mt8195-hdmi.yaml | 98 +++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml new file mode 100644 index 0000000000000..3c80bcebe6d30 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI DDC Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi-ddc + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ddc-i2c + +required: + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + hdmiddc0: ddc_i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + clock-names = "ddc-i2c"; + }; + +... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml new file mode 100644 index 0000000000000..17e542809a4e7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI Encoder Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from + its parallel input. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PLL divider + - description: PLL divider + - description: HDCP engine clock + - description: PLL divider + - description: HDCP engine clock + - description: Bus clock + - description: Clock for splitting HDMI/DGI into two pipes + + clock-names: + items: + - const: univpll_d6_d4 + - const: msdcpll_d2 + - const: hdmi_apb_sel + - const: univpll_d4_d8 + - const: hdcp_sel + - const: hdcp24_sel + - const: split_hdmi + + phys: + maxItems: 1 + + phy-names: + items: + - const: hdmi + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + - ddc-i2c-bus + +additionalProperties: false + +examples: + - | + #include + #include + hdmi0: hdmi@1c300000 { + compatible = "mediatek,mt8195-hdmi"; + reg = <0 0x1c300000 0 0x1000>; + power-domains = <&spm 25>; + clocks = <&topckgen 153>, + <&topckgen 86>, + <&topckgen 78>, + <&topckgen 146>, + <&topckgen 73>, + <&topckgen 74>, + <&vppsys1 44>; + clock-names = "univpll_d6_d4", + "msdcpll_d2", + "hdmi_apb_sel", + "univpll_d4_d8", + "hdcp_sel", + "hdcp24_sel", + "split_hdmi"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + ddc-i2c-bus = <&hdmiddc0>; + status = "disabled"; + }; + +...