From patchwork Fri Oct 22 12:19:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2FtIFNoaWggKOWPsueiqeS4iSk=?= X-Patchwork-Id: 12577655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43A3CC433F5 for ; Fri, 22 Oct 2021 12:21:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0108A6108B for ; Fri, 22 Oct 2021 12:21:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0108A6108B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BHi71HSEUO73dKa9s+iFi0/0MSEHHONGKY75RMDPVUU=; b=4KWjMqRW1IfN2I tX5BX78Y7IwVAD0Pp7qV5+cJsahItC84SpM5NUm7H0S7wNehnvER7R7I9/JIwE2/wghQAFngUghQA TPnK3AJmelbMvmCFFe/huvdBg/+lMZuAsuGV8iI2akscURwYfyC66DIRLbyHYf7lBW9SkMsYYk6oc l6WEcej5TbOo1vSPKyCeK7w05+nBx1SFubrTMgiuNwoOfgxiVkaU9J9NotgKaiLZL2UrB5EVaMnSp Lhb4OzurSH1/t7zSeEvBo67LEc7w6AUzmEZMO8bXJ6k4XRrF5ln6SnJ51WsllVx7uSvQ9/h1VW68J ihjQCTyfzrHsfxzjgjCg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdtXt-00ApTN-DR; Fri, 22 Oct 2021 12:21:13 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdtWw-00Ap0i-2e; Fri, 22 Oct 2021 12:20:15 +0000 X-UUID: 06af83188d5e4782a2647ecb1fd69f40-20211022 X-UUID: 06af83188d5e4782a2647ecb1fd69f40-20211022 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1376855522; Fri, 22 Oct 2021 05:20:13 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 22 Oct 2021 05:20:11 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 22 Oct 2021 20:20:09 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 22 Oct 2021 20:20:09 +0800 From: Sam Shih To: Rob Herring , Matthias Brugger , Michael Turquette , Stephen Boyd , Fabien Parent , "Weiyi Lu" , Chun-Jie Chen , Ikjoon Jang , Miles Chen , "Enric Balletbo i Serra" , , , , , CC: John Crispin , Ryder Lee , "Sam Shih" Subject: [PATCH v6 4/5] arm64: dts: mediatek: add clock support for mt7986a Date: Fri, 22 Oct 2021 20:19:43 +0800 Message-ID: <20211022121944.25687-5-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211022121944.25687-1-sam.shih@mediatek.com> References: <20211022121944.25687-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211022_052014_191423_17DE1A1E X-CRM114-Status: GOOD ( 11.62 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add clock controller nodes, include 40M clock source, topckgen, infracfg, apmixedsys and ethernet subsystem. Signed-off-by: Sam Shih --- v6: Used lowercase hex values in clock DT --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 68 +++++++++++++++++++++-- 1 file changed, 63 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 75912bcf6c9c..1938fab455d5 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { compatible = "mediatek,mt7986a"; @@ -13,10 +14,11 @@ / { #address-cells = <2>; #size-cells = <2>; - system_clk: dummy40m { + clk40m: oscillator@0 { compatible = "fixed-clock"; clock-frequency = <40000000>; #clock-cells = <0>; + clock-output-names = "clkxtal"; }; cpus { @@ -99,6 +101,18 @@ gic: interrupt-controller@c000000 { interrupts = ; }; + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7986-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7986-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; + }; + watchdog: watchdog@1001c000 { compatible = "mediatek,mt7986-wdt", "mediatek,mt6589-wdt"; @@ -108,11 +122,31 @@ watchdog: watchdog@1001c000 { status = "disabled"; }; + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7986-apmixedsys"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7986-sgmiisys_0", + "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7986-sgmiisys_1", + "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + trng: trng@1020f000 { compatible = "mediatek,mt7986-rng", "mediatek,mt7623-rng"; reg = <0 0x1020f000 0 0x100>; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_TRNG_CK>; clock-names = "rng"; status = "disabled"; }; @@ -122,7 +156,13 @@ uart0: serial@11002000 { "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_UART0_SEL>, + <&infracfg CLK_INFRA_UART0_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; status = "disabled"; }; @@ -131,7 +171,11 @@ uart1: serial@11003000 { "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_UART1_SEL>, + <&infracfg CLK_INFRA_UART1_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; status = "disabled"; }; @@ -140,10 +184,24 @@ uart2: serial@11004000 { "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_UART2_SEL>, + <&infracfg CLK_INFRA_UART2_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; status = "disabled"; }; + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7986-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; };