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Fri, 22 Oct 2021 12:40:55 +0000 X-UUID: cea65cb271cb4ae79c95dfd2f1da3bc5-20211022 X-UUID: cea65cb271cb4ae79c95dfd2f1da3bc5-20211022 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 985983887; Fri, 22 Oct 2021 05:40:51 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 22 Oct 2021 05:40:49 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 22 Oct 2021 20:40:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 22 Oct 2021 20:40:47 +0800 From: Sam Shih To: Linus Walleij , Rob Herring , Matthias Brugger , Sean Wang , , , , , CC: John Crispin , Ryder Lee , "Sam Shih" Subject: [PATCH v9 3/4] arm64: dts: mediatek: add pinctrl support for mt7986a Date: Fri, 22 Oct 2021 20:40:35 +0800 Message-ID: <20211022124036.5291-4-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211022124036.5291-1-sam.shih@mediatek.com> References: <20211022124036.5291-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211022_054054_440699_DEB75E6E X-CRM114-Status: GOOD ( 10.30 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add mt7986a pinctrl node, and update pinmux setting for mt7986a Signed-off-by: Sam Shih --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 20 +++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 ++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index ca074cf8e578..92e3f59c6cee 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -30,9 +30,29 @@ &uart0 { }; &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; status = "okay"; }; &uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; status = "okay"; }; + +&pio { + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 1938fab455d5..398f93385acf 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -128,6 +128,27 @@ apmixedsys: apmixedsys@1001e000 { #clock-cells = <1>; }; + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7986a-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c30000 0 0x1000>, + <0 0x11c40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", + "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 100>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + sgmiisys0: syscon@10060000 { compatible = "mediatek,mt7986-sgmiisys_0", "syscon";