@@ -530,6 +530,22 @@ &spi0 {
status = "okay";
};
+&snfi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&snfi_pins>;
+ nand-ecc-engine = <&bch>;
+ status = "disabled";
+
+ spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ nand-ecc-engine = <&snfi>;
+ };
+};
+
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic1_pins>;
@@ -497,6 +497,19 @@ spi0: spi@1100a000 {
status = "disabled";
};
+ snfi: spi@1100d000 {
+ compatible = "mediatek,mt7622-snfi";
+ reg = <0 0x1100d000 0 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_NFI_BCLK_CK_SET>,
+ <&infracfg_ao CLK_INFRA_AO_NFI_INFRA_BCLK_CK_SET>,
+ <&infracfg_ao CLK_INFRA_AO_NFI_HCLK_CK_SET>;
+ clock-names = "nfi_clk", "snfi_clk", "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
thermal: thermal@1100b000 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt7622-thermal";
Add snfi node for SPI NAND controller. Just take MT7622 for example at present. Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 13 +++++++++++++ 2 files changed, 29 insertions(+)