From patchwork Wed Jan 12 11:55:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 12711313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6EFF9C433EF for ; Wed, 12 Jan 2022 11:58:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=udk69cuqCf+GoynzJ6r675qQcK03LJmaB7up/1mTP3U=; b=Vdfsi4ODbSTtO1 OW6mC1Br2rlqQCqim3gfXG/g4v1cgTtEWlFv2yojpBe+lT87icXRtikGJ5HCTq4LCfgUCTVvoy9Ef xORzcS3ZxHjN2yN4DzVw4kZju2Jfj6ED4DkGq64Gnz5sfsCQYsLlqBSCk7IhxGJYl1MuXPt+i0HHn A6NDf6bRaG6cpWRLj9/zOQRSzmSeCF22gkDZj3fT8H2hDHUNjmRbcoiH3sgc2MlXUOf1n9bUZv1w9 PQ0F7B0l4F47+PH9EbJWE+zYwqZeNEsKPwQI4OPUdMcMYWI25VkCca2Szic3pdd2w3fpS8HDrLRgy HWgAWTs9mIpR/5X5fS7w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7cGy-002PRq-Ba; Wed, 12 Jan 2022 11:58:36 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7cGO-002PBB-HL; Wed, 12 Jan 2022 11:58:01 +0000 X-UUID: 8febc3e6cea348e9b54d36a8ca382613-20220112 X-UUID: 8febc3e6cea348e9b54d36a8ca382613-20220112 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1557990102; Wed, 12 Jan 2022 04:57:56 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Jan 2022 03:55:46 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 12 Jan 2022 19:55:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 12 Jan 2022 19:55:44 +0800 From: allen-kh.cheng To: Matthias Brugger , Rob Herring , CC: , , , , , , , , Chen-Yu Tsai , Ryder Lee , Allen-KH Cheng Subject: [PATCH v3 1/5] arm64: dts: mediatek: Correct uart clock of MT8192 Date: Wed, 12 Jan 2022 19:55:38 +0800 Message-ID: <20220112115542.10606-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220112115542.10606-1-allen-kh.cheng@mediatek.com> References: <20220112115542.10606-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220112_035800_608772_F32E8496 X-CRM114-Status: GOOD ( 14.15 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Allen-KH Cheng When the initial devicetree for mt8192 was added in 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile"), the clock driver for mt8192 was not yet upstream, so the clock property nodes were set to the clk26m clock as a placeholder. Given that the clock driver has since been added through 710573dee31b ("clk: mediatek: Add MT8192 basic clocks support"), as well as its dt-bindings through f35f1a23e0e1 ("clk: mediatek: Add dt-bindings of MT8192 clocks") and devicetree nodes through 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers"), fix the uart clock property to point to the actual clock. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c7c7d4e017ae..cfb67cc40c2c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -327,7 +327,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; clock-names = "baud", "bus"; status = "disabled"; }; @@ -337,7 +337,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; clock-names = "baud", "bus"; status = "disabled"; };