| Message ID | 20220126090109.32143-1-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: mt8195: add gce node | expand |
Il 26/01/22 10:01, jason-jh.lin ha scritto: > Add gce node and gce alias on mt8195 dts file. > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > This patch is based on [1] > > [1] arm64: dts: Add mediatek SoC mt8195 and evaluation board > - https://patchwork.kernel.org/project/linux-mediatek/patch/20220112114724.1953-4-tinghan.shen@mediatek.com/ > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index a363e82f6988..d778ca598d18 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -6,6 +6,7 @@ > > /dts-v1/; > #include <dt-bindings/clock/mt8195-clk.h> > +#include <dt-bindings/gce/mt8195-gce.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/interrupt-controller/irq.h> > #include <dt-bindings/phy/phy.h> > @@ -18,6 +19,11 @@ > #address-cells = <2>; > #size-cells = <2>; > > + aliases { > + gce0 = &gce0; > + gce1 = &gce1; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -367,6 +373,22 @@ > assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; > }; > > + gce0: mdp_mailbox@10320000 { Just "mailbox" is fine. gce0: mailbox@10320000 { > + compatible = "mediatek,mt8195-gce"; > + reg = <0 0x10320000 0 0x4000>; > + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; > + #mbox-cells = <2>; > + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; > + }; > + > + gce1: disp_mailbox@10330000 { Same here, please. After that, Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + compatible = "mediatek,mt8195-gce"; > + reg = <0 0x10330000 0 0x4000>; > + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; > + #mbox-cells = <2>; > + clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; > + }; > + > scp_adsp: clock-controller@10720000 { > compatible = "mediatek,mt8195-scp_adsp"; > reg = <0 0x10720000 0 0x1000>; >
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index a363e82f6988..d778ca598d18 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/clock/mt8195-clk.h> +#include <dt-bindings/gce/mt8195-gce.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/phy/phy.h> @@ -18,6 +19,11 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + gce0 = &gce0; + gce1 = &gce1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -367,6 +373,22 @@ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; }; + gce0: mdp_mailbox@10320000 { + compatible = "mediatek,mt8195-gce"; + reg = <0 0x10320000 0 0x4000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; + }; + + gce1: disp_mailbox@10330000 { + compatible = "mediatek,mt8195-gce"; + reg = <0 0x10330000 0 0x4000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8195-scp_adsp"; reg = <0 0x10720000 0 0x1000>;
Add gce node and gce alias on mt8195 dts file. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> --- This patch is based on [1] [1] arm64: dts: Add mediatek SoC mt8195 and evaluation board - https://patchwork.kernel.org/project/linux-mediatek/patch/20220112114724.1953-4-tinghan.shen@mediatek.com/ --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)